本論文提出一個結合雜訊整型逐漸逼近式類比數位量化器之2-1多級串疊三角積分調變器。在以往的設計中，欲完成一個高速且高解析的三角積分調變器(SDM)，必須提昇量化器的位元數且在不增加超取樣比率(oversampling ratio, OSR)的情況下，增加雜訊整型(noise-shaping)的階數。我們將具雜訊整型能力之逐漸逼近式類比數位量化器(noise-shaping quantizer)應用於實現多級串疊三角積分調變器(MASH)的第一級和第二級量化器(quantizer)，不但提升了雜訊整型的階數，有效的減少多級串疊三角積分調變器因不匹配所造成的影響，並減少運算放大器的使用數量。
本設計以台積電90奈米CMOS製程實作測試晶片，晶片面積為1.6416毫米平方。當晶片操作在輸入電壓1.0伏特下，取樣頻率為每秒八千萬次，頻寬可達三百萬赫茲；當輸入訊號頻率為一百萬赫茲時，量測得到的訊號雜訊失真比(SNDR)達71.44 dB；晶片總共消耗19.91毫瓦，可換算得到轉換效率(FOM)為153.67 dB。觀察傅立葉轉換後的波形，高頻雜訊的斜率介於40 dB/dec和60 dB/dec之間，結果顯示為接近三階的雜訊整型，成功驗證所提之設計架構與技術。

This work presents a noise-shaping SAR assisted MASH 2-1 sigma-delta modulator. In previous designs, to implement a SDM with high resolution and high speed, the resolution of the quantizer has to be increased and the noise-shaping order must be raised with a fixed oversampling ratio (OSR). We have combined the first-stage and second-stage quantizers of the MASH into a noise-shaping quantizer. By combining the presented architecture and the quantizer, not only the noise-shaping order is raised, but also the number of OPAMPs and the mismatch effect between the first stage and the second stage can be reduced.
The proof-of-concept prototype was fabricated in TSMC 90-nm CMOS technology, and the chip occupies 1.6416 mm2. As the prototype operates at a supply voltage of 1.0-V, sampling rate of 80-MS/s, bandwidth of 3.333 MHz and input frequency of 1 MHz, the measurement result shows it can achieve 71.44 dB SNDR with the power consumption being 19.91 mW, and the Figure of Merit (FoM) is 153.67 dB. By observing the spectrum after FFT computation, the slope of it is between 40 dB/dec and 60 dB/dec, which verifies the almost 3rd noise-shaping successfully.

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