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研究生： 張孫偉
Chang, Sun-Wei
論文名稱： 高階加密演算法(AES)超大型積體電路設計與實現
VLSI Architectures and FPGA Implementation for Universal AES Crypto-processor
指導教授： 王駿發
Wang, Jhing-Fa
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2003
畢業學年度： 91
語文別： 英文
論文頁數： 99
中文關鍵詞： 高階加密演算法
外文關鍵詞： Cipher, Advanced Encryption Standard, AES
相關次數： 點閱：78  下載：3 
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    • Sun-Wei Chang* Jhing-Fa Wang**
    Department of Electrical Engineering
    National Cheng Kung University, Tainan, Taiwan, R.O.C.

    This thesis presents an Intellectual Property (IP) core of the entire Advanced Encryption Standard (AES) algorithm[1]. Our design utilizes the T-Box algorithm to implement the Rijndael round function[2]. By analyzing the pipelining data flow, a new architecture, which combines the multiplexing and the iteration architecture, is also proposed. The designs are implemented using the Integrated Systems Engineering (ISE) 5.1i software [3] on a single Virtex-E XCV812E [4] Field Programmable Gate Array (FPGA) device. As a result, the AES IP core operates at 61MHz with the key scheduler resulting in a throughput of 1.9Gbps for the AES encryption and decryption with the block size of 128 bits and the flexible key size. Finally, comparison is provided between our design and similar existing implementations.
    * The author
    ** The advisor

    Abstract v Contents vi Acknowledgement x List of Figures xi List of Tables xiv Chapter 1 Introduction 1 1.1 Information Security and Symmetric-Key Cryptography 1 1.2 Overview of the AES Development 1 1.3 Related Works on AES Crypto Core 2 1.4 SOC and AMBA 3 1.5 Applications 4 1.6 Organization of This Thesis 4 Chapter 2 AES Algorithm 6 2.1 Definition 6 2.1.1 Glossary of Terms and Acronyms 6 2.1.2 Algorithm Parameter, Symbols, Terms, and Functions 7 2.2 Notation and Conventions 8 2.2.1 Inputs and Outputs 8 2.2.2 Bytes 9 2.2.3 Array of Bytes 10 2.2.4 The State 11 2.2.5 The State as An Array of Columns 12 2.3 Algorithm Specification 12 2.3.1 Cipher 14 2.3.1.1 SubBytes() Transformation 15 2.3.1.2 ShiftRows() Transformation 16 2.3.1.3 MixColumns() Transformation 17 2.3.1.4 AddRoundKey() Transformation 18 2.3.2 Key Expansion 19 2.3.3 Inverse Cipher 21 2.3.3.1 InvSubBytes() Transformation 22 2.3.3.2 InvShiftRows() Transformation 22 2.3.3.3 InvMixColumns() Transformation 23 2.3.3.4 Inverse of the AddRoundKey() Transformation 24 2.3.3.5 Equivalent Inverse Cipher 24 2.4 T-Box Algorithm 26 2.4.1 Modification of the Order of Operations 26 2.4.2 Table Look-up Based on T-box 27 Chapter 3 Design Methodologies and VLSI Architectures 30 3.1 Design Considerations 30 3.2 Design Methodologies 30 3.3 Pipelining Analysis for the AES Algorithm 32 3.4 The Overall Architecture of our AES Core 34 3.5 AHB Slave Finite State Machine 35 3.6 Round Path 37 3.6.1 Input Register 37 3.6.2 Output Register 38 3.6.3 Initial Round 38 3.6.4 Final Round 39 3.6.5 Round Unit and Finite State Machine 41 3.6.6 Round Unit Bank 43 3.7 Key Path 44 3.7.1 Key Generator 45 3.7.2 InvMixCloumn 48 3.7.3 Key Banks 49 Chapter 4 Experiment Results 51 4.1 Tools and Devices Used for Implementations 51 4.2 Design Flow and Strategy 52 4.3 Simulation Result 52 4.3.1 Behavioral Verilog Module Simulation 53 4.3.2 Post-Place & Route Verilog Module Simulation 54 4.4 Crypto Core Pin Description 55 4.5 Chip Feature and Layout View 57 4.6 Related Work Analysis and Comparison 59 Chapter 5 Conclusions 61 Appendix I 62 Appendix II 67 References 76 Biography 85

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