在單晶片或混合訊號系統中，鎖相迴路電路為一個重要的建構單元。鎖相迴路的應用很多如：去除時脈偏斜、降低時脈抖動，頻率合成與時脈資料回復等等。但隨著鎖相迴路應用的快速成長，設計複雜度的增加，鎖相迴路的測試變得相當困難，值得去重視。
對於鎖相迴路而言，時脈抖動是一個重要的參數，時脈抖動定義為正確時脈轉換時間點的誤差。在量測時脈抖動時，通常需要昂貴的測試儀器，所以本論文提出一個簡單的架構來偵測時脈抖動。在有時脈抖抖動發生時的狀況紀錄在一錯誤計數器中。之後，並得到一個錯誤次數的累積統計圖，經由分析此統計圖即可求得時脈抖動方均根值。本測試電路並沒有連接到鎖相迴路中易受影響的節點，所以並不會對電路效能有所影響 。
此外，我們亦設計操作範圍在600~900MHz的鎖相迴路，採用TSMC 0.35um的製程技術實現，以便和測試電路整合，達到內建自我測試的目標

In an SOC or a mixed-mode system, a phase-locked loop (PLL) is an important building block which provides many useful applications such as skew suppression, jitter reduction, frequency synthesizing, and clock and data recovery. With the variety of PLL applications and the increase of the design complexity, the testing of PLL has become a critical problem in SOC testing.
Jitter is a key parameter of a PLL and is defined as the deviation from the precise clock transition. Conventionally it needs an expensive Automatic Test Equipment (ATE) for jitter measurement. In this thesis, we propose a simple on-chip architecture to detect this timing error. If a timing error occurs, it is recorded in an error counter. Then a statistical chart of the error count can be plotted and the root-mean-square (RMS) value of the jitter can be obtained by analyzing the statistical chart. In our design, the test circuits do not access the sensitive nodes in the PLL circuit and will have minimum impact on the PLL performance.
We implement a PLL in order to integrate it with our test architecture and to verify our testable design the purpose of BIST. The range of the operating frequency of the PLL is 600~900MHz. The PLL is implemented using the TSMC 0.35um1P4M technology.

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