基於摩爾定律經驗下，半導體技術與製程發展持續不斷的演進，晶片也隨之微小化、多樣化與複雜化。由於現今的積體電路在設計上、製造上以及相關測試驗證的流程不僅耗時也同時伴隨著急速攀升的成本支出，如何保障每顆生產的晶片都可以正常的工作且具有良好的可靠度，進而降低生產及測試成本支出以獲得穩定的利潤已經是十分重要的一門課題。西元2002年，國際知名半導體製造商IBM首度對外發表了電子編程熔絲(Electrically Programmable Fuse, eFuse)的技術文件。IBM成功將電致遷移效應實現於eFuse元件，即使該效應在傳統半導體製程當中一直是被視為可靠度與電路設計的不良缺陷。西元2004年，IBM在12吋半導體製程正式將eFuse技術應用在其所設計與製造的微處理器之中。直至現今，eFuse已經是廣為使用在半導體金氧半(Complementary metal-oxide-semiconductors, CMOS)製程中的技術，亦為一次性編程(One-time Electrically Programming, OTP) 應用之中發展快速且為人熟知的元件。從該技術發表至今，國內外已經累積不少其相關的研究論文，不論是在電性上或物性上，針對其編程機制以及不同材質與結構都有極深入之探討。本論文根據該技術主要分為兩個主題進行研究，第一個主題針對多晶矽電子編程熔絲(Polysilicon eFuse)進行相關實驗與討論，第二個主題則是主動區電子編程熔絲(Active eFuse)的試作與研究。

首先，針對多晶矽電子編程熔絲的研究，此部分分為兩個實驗，第一個實驗使用了相容於雙重應力介層(Dual-stress-liner, DSL)的CMOS製程技術製備具有不同應力環境下的多晶矽電子編程熔絲，其一為壓縮應力(Compressive-stress)薄膜，其二為拉伸應力(Tensile-stress)薄膜，並探討其特性與效能。第二個實驗則是使用了相容於單一應力介層(Single-stress-liner, SSL)的CMOS製程技術，藉由選擇性的加入應力緩衝層(Stress buffer layer)，製備具有不同應力環境下的多晶矽電子編程熔絲。經由電性上的量測分析與物性上的穿透式電子顯微鏡(Transmission electron microscopy, TEM) and 能量色散X-射線光譜(Energy dispersive X-ray spectrometry, EDS)分析，其編程機制，如電致遷移模式(Electromigration mode)與多晶矽斷裂模式(Polysilicon Rupture mode)，得已被充分的討論與理解。該實驗結果顯示具有壓縮應力的薄膜或有效的降低具有拉伸應力的薄膜施加在電子熔絲上的應力，皆有助於提升多晶矽電子編程熔絲在編程後的可靠度與性能表現，這是由於壓縮應力可促成空洞成核反應(void nucleation)，進而使得多晶矽產生完整的斷裂部，除了可有效增加熔絲電阻，並同時可防止融熔態之矽化金屬化合物在編程過程中因為容積變化產生之反作用力所形成的回填現象，由第一個實驗成果可得最低與最高的編程電流為7 mA與13 mA，並同時達到編程後與編程前的電阻比大於10^3，而第二個實驗成果可得最低與最高的編程電流為5 mA與10 mA，而編程後與編程前的電阻比大於10^2。

另外，針對主動區電子編程熔絲的研究，則是使用了具有絕緣層的矽晶圓(SOI wafer)來製備，由於該晶圓的主動區與矽基板使用了絕緣層作為隔離，可有效阻隔矽基板產生的熱傳導，因此十分適合用以製造主動區電子編程熔絲。在該實驗中，使用了不同摻雜型態的熔絲，一為N型，一為P型。從結果得知，P型主動區電子編程熔絲具有較佳的特性，這是由於P型摻雜有助於矽化金屬層與主動區的電致遷移效應，進而產生主動區的斷裂或斷開現象，該現象有助於提升編程後的熔絲電阻，實驗成果可得最低與最高的編程電流為16 mA與22 mA，同時達到編程後與編程前的電阻比大於10^3。

Under the guidance of Moore's Law, the manufacturing semiconductor process of integrated circuits has been going forward. And the complexity of IC chips has been also greatly increased. How to ensure each IC workable and prevent it from failure is a big topic because the cost of IC design and semiconductor manufacturing has been increased radpidly. In 2002, the Electrically Programmable Fuse (eFuse) technology was originally published in an IBM's technical paper at embedded DRAM conference. It has successfully adopted electromigration into semiconductor manufacturing even electromigration technology has traditionally had an adverse effect on wafer performance and has been avoided in design. And IBM announced that e-Fuse is successfully implemented into semiconductor circuit of its micro-processors on 300mm fabrication in 2004. Now, this eFuse has been a popular one of current one-time electrically programmable (OTP) components and widely adopted into complementary metal-oxide-semiconductors (CMOS) related semiconductor chips from 0.25um and beyond. In recent years, Many studies have discussed the programming conditions and physical characteristics of different eFuse structures. This dissertation is divided into two main parts to study different eFuse structures. The first part is the related research about polysilicon eFuse, and the second one is about active eFuse.

In the part of polysilicon eFuse studies, the characterization and performance of an electrically programmable fuse (eFuse) prepared with compatible fabrication processes for complementary metal-oxide-semiconductors (CMOS) manufacturing combined with dual-stress-liner (DSL) or single-stress-liner (SSL) technique are discussed. According to the 1st experimental result, the preapred polysilicon fuse capped with compressive-stress or tensile-stress film show different electrical and physical behaviors. The programming mechanism included electromigration mode (EM) and rupture mode (RM) is well performed by referring to the analysis of transmission electron microscopy (TEM) and energy dispersive X-ray spectrometry (EDS). And the use of stress buffer layer in 2nd experiment is also studied to mitigate the intensity of the tensile-stress film. Based on the theories of electromigration, stress-migration and Blech effect, the compressive-stress film is found to contribute to void nucleation which not only increases the programmed fuse resistance but also acts as a silicide-layer refill inhibitor to provide more reliable programmed eFuse functionality. Finally, 1st experiment shows that the minimum and maximum programming currents are 7 mA and 13 mA with the ratio of post-programmed resistance (Rf) to the unprogrammed resistance (Ri), >10^3. And 2nd experiment has the minimum and maximum programming currents as 5 mA and 10 mA with the Rf/Ri ratio, >10^2.

In the last research of active eFuse, an active fuse is successfully implemented in an SOI process fully compatible with the current CMOS technology. The structure of SOI inherently provides an isolation environment for active eFuse and is helpful to the thermal effect. The programming performance is studied with regard to the doping type of the diffusion layer. The P-type active fuse was observed to have better programming performance than the N-type at both room and high temperatures. The formation of diffusion break after programming assists the performance of the P-type active fuse. Finally, this experiment shows that the minimum and maximum programming currents are 16 mA and 22 mA with the Rf/Ri ratio, >10^3.

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