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研究生： 王建勛
Wang, Chien-Hsun
論文名稱： 砷化銦/銻化砷鋁磊晶層和高介電值閘極氧化物在砷化銦基板上之研究
Study of InAs/AlAsSb Epi-Layers and High-k Gate Dielectrics on InAs Substrate
指導教授： 許渭州
Hsu, Wei-Chou
學位類別： 博士
Doctor
系所名稱： 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年： 2014
畢業學年度： 102
語文別： 英文
論文頁數： 125
中文關鍵詞： 鰭型場效電晶體 、原子層沉積 、介面陷阱密度 、沉積後的退火 、介面覆蓋層 、氧化終止
外文關鍵詞： FinFET, ALD, Dit, PDA, ICL, Oxygen termination
相關次數： 點閱：77  下載：0 
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    • 三五族半導體材料基於其高注射速度，可以在未來的技術使用中增加驅動電流，目前已被考慮應用在互補式金氧半導體。在晶格常數約為6.1埃的N型及P型場效電晶體中，以砷化銦(能隙為0.35電子伏特)和銻化鎵(能隙為0.73電子伏特)為基礎的通道在操作電壓為0.5伏特的應用中脫穎而出。本論文中，將探討有機金屬氣相沉積成長砷化銦、銻化鎵/銻化砷鋁及砷化銦/銻化砷鋁，暨研究高介電值閘極氧化物在砷化銦及砷化銦/銻化砷鋁介面。
    利用三五比和成長溫度的最佳化，來探究有機金屬氣相沉積成長(100)和(110)晶格方向的砷化銦，並利用此兩個晶格方向製成的金氧半導體電容，來研究鰭型場效電晶體在兩個通道方向的介面，從氧化鋁和氧化鉿在兩個晶格方向製成的金氧半導體電容之物理和電氣特性研究中，得到相當類似的介面陷阱密度。此外，也發表了利用有機金屬氣相沉積成長銻化鎵/銻化砷鋁/砷化銦和砷化銦/銻化砷鋁/砷化銦的異質結構，這個高品質的結構已透過X射線繞射分析儀中小於一百弧度秒的半高寬驗證，此外，也可以觀察到清晰且段落分明的Pendellösung條紋，並在高解析度穿透式電子顯微鏡中看到無缺陷的介面，從量產的觀點而言，這種結果顯示了三五族取代矽通道的可能性。
    改善介面陷阱密度的實驗包含了在原子層沉積前的外部及內部預先處置，鈦化金、鈀、鉑的閘極金屬，原子層沉積後的退火，原子層沉積的溫度和噴入及清淨的時間，以及導入介面覆蓋層用來改變介面陷阱密度的分布等，實驗結果顯示了改善介面陷阱密度的主要因子為原子層沉積的溫度。在砷化銦表面做氧化終止和低溫原子層沉積的氧化鉿，可以讓高介電值閘極氧化物在砷化銦介面的陷阱密度改善40倍，在砷化銦能隙中2.2 × 1011的介面陷阱密度可以展現元件等級的品質，在此介面陷阱密度下，電容-電壓曲線趨於正常符合預期模式，同時也可以觀察到電洞反轉的現象。

    III-V semiconductor materials are currently considered for CMOS implementation based on their attractive injection velocities that may help to increase the drive current in future technology nodes. InAs (bulk bandgap Eg = 0.35 eV) and GaSb (Eg = 0.73 eV) based channels are contenders at Vd of 0.5 V with both nFET and pFET channels implemented utilizing materials within the same range of lattice constant (6.1 Å). In this dissertation, we studied the MOCVD growth for the InAs, GaSb/AlAsSb, and InAs/AlAsSb on native substrates and the interface of high-k gate dielectrics on InAs and InAs/AlAsSb.
    The investigation of MOCVD growth for (100) and (110) InAs epitaxy on native substrates was done by optimizing V/III ratio and growth temperature. The following (100) and (110) InAs MOSCAP fabrication was for the interface study using InAs channel and non-planar device architecture like FinFET, consisting of two surface planes including the (100) and (110) planes. The physical and electrical characterization of Al2O3 and HfO2 on (100) and (110) n-InAs epi surfaces showed similar interface trap density (Dit) on (100) and (110) surface orientation. Therefore, GaSb/AlAs0.16Sb0.84/InAs and InAs/AlAs0.16Sb0.84/InAs heterostructures grown by MOCVD were presented. The excellent quality of the structures was confirmed by XRD rocking curves with FWHMs below 100 arc seconds for AlAs0.16Sb0.84, clear and crisp Pendellösung fringes, and HRTEM showing defect-free interfaces. From a production point of view, this demonstration shows the possibility that III-V's could replace the Si channel.
    Experiments for reducing Dit including ex-situ and in-situ pre-treatments before ALD, gate metal splits with Ti/Au, Pd, and Pt, post deposition anneal (PDA) splits after ALD, splits for ALD deposition temperature and pulse/purge time, and introducing interface cap layer (ICL) for changing Dit distribution profile showed the major factor is the ALD process temperature. InAs surface oxygen termination and low temperature atomic layer deposition of HfO2 showed improved interface trap density Dit at the high-k/InAs interface by >40× by interface engineering. With a Dit of 2.2 × 1011 cm-2 eV-1 within the InAs bandgap, device quality has been demonstrated, with C-V curves approaching normal and expected behavior, and observation of hole inversion.

    摘 要 I Abstract III 致 謝 V Content VI Figure Captions IX Table Captions XV Chapter 1 Introduction 1 1.1 Background 1 1.2 Introduction of InAs channel 1 1.3 High-k gate dielectrics 2 1.4 Introduction of atomic layer deposition (ALD) 3 1.5 Interface trap density (Dit) calculation 4 1.6 Introduction of InAs/AlAs0.16Sb0.84 heterostructure device 5 1.7 Overview of this dissertation 5 Chapter 2 The epitaxial growths of InAs, GaSb/AlAs0.16Sb0.84, and InAs/AlAs0.16Sb0.84 on InAs substrate by MOCVD 7 2.1 Introduction of the MOCVD system 7 2.1.1 Metal-Organic and Hydride sources used in this dissertation 8 2.2 Investigation of (100) and (110) InAs epitaxial growths by MOCVD 8 2.2.1 (100) InAs epitaxial growth by MOCVD 9 2.2.2 (110) InAs epitaxial growth by MOCVD 11 2.3 The epitaxial growths of GaSb/AlAs0.16Sb0.84 and InAs/AlAs0.16Sb0.84 on (100) InAs substrate by MOCVD 13 2.3.1 Experimental details 14 2.3.2 Source materials and precursor consideration 14 2.3.3 AlAs0.16Sb0.84 growth on (100) InAs substrate 16 2.3.4 PL and SIMS of AlAs0.16Sb0.84 on InAs 17 2.3.5 Epitaxial growth and characterization of heterostructures 18 2.3.6 Growth of GaSb/AlAs0.16Sb0.84/InAs heterostructures 18 2.3.7 Growth of InAs/AlAs0.16Sb0.84/InAs heterostructures 19 2.3.8 Summary 20 Chapter 3 High-k dielectrics on (100) and (110) n-InAs: Physical and Electrical Characterization 22 3.1 Introduction 22 3.2 MOSCAP fabrication process 23 3.3 Experiments 23 3.4 Physical characterization for high-k dielectrics on (100) and (110) n-InAs 24 3.5 Electrical characterization and Dit extraction for high-k dielectrics on (100) and (110) n-InAs 25 3.6 Summary 28 Chapter 4 High-k dielectrics on (100) n-InAs MOSCAPs: Experiments and Process optimization for Dit reduction 29 4.1 Introduction 29 4.2 Capacitance-Voltage (C-V) parameterization 29 4.3 The introduction of slow hole traps density 31 4.4 Experiments for ex-situ and in-situ pre-treatment before ALD 31 4.5 Experiments for the MOSCAP gate metal splits with Pd, Ti/Au, and Pt 32 4.6 Experiments for the splits of post deposition anneal (PDA) after ALD process ………………………………………………………………………………..32 4.7 Experiments for the splits of ALD deposition temperature and pulse/purge time 33 4.8 Experiments for interface cap layer (ICL) by InP cap on InAs epitaxy 33 4.9 Conclusion 34 Chapter 5 InAs hole inversion and bandgap interface trap density of 2 × 1011 cm-2 eV-1 at HfO2/InAs and HfO2/InAs/AlAs0.16Sb0.84 interfaces 36 5.1 Introduction 36 5.2 Sample preparation and fabrication for MOSCAPs 36 5.3 C-V measurement and Dit extraction for MOSCAPs 38 5.4 Conclusions 40 Chapter 6 Conclusions and Future works 41 6.1 Conclusions 41 6.2 Future works 41 References 43 Vita 123 Publication List 124

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