| 研究生: |
楊佩蓉 Yang, Pei-Jung |
|---|---|
| 論文名稱: |
具定頻及最佳化暫態響應之數位控制漣波模式降壓轉換器 Digital Ripple Control to Achieve Constant-Frequency and Optimized Transient for Buck Converter |
| 指導教授: |
張簡樂仁
Chang-Chien, Le-Ren |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2021 |
| 畢業學年度: | 109 |
| 語文別: | 中文 |
| 論文頁數: | 106 |
| 中文關鍵詞: | 適應性導通時間控制法 、漣波模式控制降壓轉換器 |
| 外文關鍵詞: | Adaptive on-time control, ripple-based buck converter |
| 相關次數: | 點閱:253 下載:0 |
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漣波控制模式降壓轉換器常出現系統穩定度、穩態誤差、操作頻率變動的現象。一般採用類比電路解決上述問題仍面臨製程飄移或晶片老化影響元件參數而降低其效果,反觀數位電路即便面臨晶片老化只要高低準位仍正常判定,則不影響電路功能。本電路採用電容電流偵測微分器改善因輸出電容之低等效串聯電阻造成的脈波爆裂現象;自動電壓準位修正電路調整因漣波訊號造成的電壓偏移;全數位定頻導通時間控制法來實現固定切換頻率,透過占空比來調整導通時間,使操作頻率穩定於額定規格;透過數位最佳暫態控制法縮短暫態安定時間。
本文以FPGA ADC-SoC開發板及PCB電路分別實現數位電路及類比電路。降壓轉換器輸入電壓與輸出電壓分別為4.2V及1.2V,在負載電流變動範圍為100~500mA下,加入定頻機制使得操作頻率變動量由40%降低至2.8%,電壓準位偏移降低至0.3%,而數位最佳暫態控制縮短了升載及降載響應的安定時間至3μs以內,其性能係數(Figure of merit)與其他相關先進技術相比具有優勢。
A ripple-controlled buck converter typically suffers from circuit instability, a steady-state error, and variations in the switching frequency. The conventional analog approaches used to solve these problems still encounter intrinsic parameter drifting due to the manufacturing process and circuit aging, which undermine the performance of the original system. On the other hand, the same problem does not occur with a digital circuit design. The proposed rip-ple control implements a capacitor current sensor differentiator to retrieve the ripple signal from a low ESR output capacitor. This approach makes it possible to avoid pulse bursting phenomena that could degrade circuit stability. In addition, an auto-correct voltage offset circuit can adjust the voltage bias produced by the ripple signal so that steady voltage offset can be minimized. An all-digital constant-frequency on-time control can stabilize the switch-ing frequency under variable loading conditions during steady state. A digital time optimized control is implemented to shorten the settling time during the load transient period.
The concept of the digital ripple control was implemented using an FPGA (field-programmable gate array) and validated on a PCB (printed circuit board). The input and output voltages of the buck converter were 4.2V and 1.2V, respectively. Under load cur-rent changes ranging between 100 and 500 mA, variations in the switching frequency de-creased from 40% to 2.8%, and the output voltage offset decreased to 0.3%. The settling times were shortened to within 3μs. The figure of merits (FOMs) were comparable to those found in prior studies.
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