隨著製程技術的進步，單一晶片已經可以包含數百萬顆電晶體，進而導致系統中的漏電流功耗 (leakage power) 越來越惡化的問題日益嚴重。雖然power gating是減少漏電流功耗最有效率的技術之一，然而，設計者對睡眠電晶體尺寸的調整仍然是一個問題。對於power gating，調整睡眠電晶體的尺寸是power gating最關鍵的問題，因為它會顯著的影響漏電流功耗以及系統效能。為了尋找出最適合系統、最小的電晶體尺寸，以往許多文獻從各方面提出了有效調整電源閘控電晶體尺寸的演算法。然而，效果越好的演算法，所花費的執行時間卻越久。基於這樣的觀察，本論文提出了限界平行疊代演算法 (bounded parallel iterative algorithm)，可以同時降低演算法的執行時間以及減少總睡眠電晶體的尺寸。
本論文所提出的演算法與效果最好的文獻 [28] 的V-TPC演算法相比，平均可降低77倍的演算法執行時間，減少20%的電源閘控電晶體尺寸，以及節省20%的漏電流功耗。

With the advancement of semiconductor process technology, millions of transistors could be integrated into single chip, which, subsequently, make the system leakage power consumption an increasingly worsen problem. Although power gating is one of the most efficient techniques to reduce the leakage power, sleep transistor sizing remains an issue to designers. Sizing the sleep transistors is the most critical concern for power gating because it significantly affects the leakage reduction and circuit performance. In order to find the most suitable and smallest transistor size, many previous researches presented efficient algorithms from all aspects. However, the better the algorithm is, the more execution time it takes. In this thesis, we propose a bounded parallel iterative algorithm that can reduce the execution time and the total sizes of sleep transistors simultaneously.
The proposed algorithm achieves 77 times reduction in execution time, decrease power gating transistor size and leakage power by 20% and 20%, respectively, when compared with state-of-the-art approach V-TPC [28].

[1] N. S. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, and V. Narayanan, "Leakage current: Moore's law meets static power," Computer, vol. 36, no. 12, pp. 68-75, 2003.
[2] R. R. Rao, A. Devgan, D. Blaauw, and D. Sylvester, "Parametric yield estimation considering leakage variability," in Proc. IEEE/ACM Design Automation Conference (DAC), 2004, pp. 442-447.
[3] H. l. Chang and S. S. Sapatnekar, "Full-chip analysis of leakage power under process variations, including spatial correlations," in Proc. IEEE/ACM Design Automation Conference (DAC), 2005, pp. 523-528.
[4] N. S. Kim, D. Blaauw, and T. Mudge, "Quantitative analysis and optimization techniques for on-chip cache leakage power," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 13, no. 10, pp. 1147-1156, 2005.
[5] B. H. Calhoun, F. A. Honore, and A. P. Chandrakasan, "A leakage reduction methodology for distributed MTCMOS," IEEE J. Solid-State Circuits (JSSC), vol. 39, no. 5, pp. 818-826, 2004.
[6] Z. Liu and V. Kursun, "Charge Recycling MTCMOS for Low Energy Active/Sleep Mode Transitions," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2007, pp. 1389-1392.
[7] M. Keating, D. Flynn, R. Aitken, and K. Shi, Low power methodology manual: for system-on-chip design: Springer, 2007.
[8] S. Kaijian and D. Howard, "Challenges in sleep transistor design and implementation in low-power designs," in Proc. IEEE/ACM Design Automation Conference (DAC), 2006, pp. 113-116.
[9] K. Shi and D. Howard, "Sleep Transistor Design and Implementation - Simple Concepts Yet Challenges To Be Optimum," in Proc. IEEE Int. Symp. on VLSI Design, Automation and Test (VLSI-DAT), 2006, pp. 1-4.
[10] B. Kapoor, S. Hemmady, S. Verma, K. Roy, and M. A. D'Abreu, "Impact of SoC power management techniques on verification and testing," in Proc. Int. Symp. Quality Electronic Design (ISQED), 2009, pp. 692-695.
[11] S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE J. Solid-State Circuits (JSSC), vol. 30, no. 8, pp. 847-854, 1995.
[12] S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, "A 1-V high-speed MTCMOS circuit scheme for power-down application circuits," IEEE J. Solid-State Circuits (JSSC), vol. 32, no. 6, pp. 861-869, 1997.
[13] S. Idgunji, "Case study of a low power MTCMOS based ARM926 SoC : Design, analysis and test challenges," in Proc. IEEE Int. Test Conference (ITC), 2007, pp. 1-10.
[14] H. Kawaguchi, K. I. Nose, and T. Sakurai, "A CMOS scheme for 0.5 V supply voltage with pico-ampere standby current," in Proc. IEEE Int. Solid-State Circuits Conference (ISSCC), 1998, pp. 192-193, 436.
[15] T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, and T. Sakurai, "Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration," in Proc. IEEE Custom Integrated Circuits Conference (CICC), 2000, pp. 409-412.
[16] C. Y. Chang, W. B. Yang, C. J. Huang, and C. H. Chien, "New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2007, pp. 3740-3743.
[17] J. Le Coz, P. Flatresse, S. Engels, A. Valentian, M. Belleville, C. Raynaud, D. Croain, and P. Urard, "Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec," in Proc. IEEE Int. Solid-State Circuits Conference (ISSCC), 2011, pp. 336-337.
[18] J. W. Tschanz, S. G. Narendra, Y. Ye, B. A. Bloechel, S. Borkar, and V. De, "Dynamic sleep transistor and body bias for active leakage power control of microprocessors," IEEE J. Solid-State Circuits (JSSC), vol. 38, no. 11, pp. 1838-1845, 2003.
[19] J. Kao, S. Narendra, and A. Chandrakasan, "MTCMOS hierarchical sizing based on mutual exclusive discharge patterns," in Proc. IEEE/ACM Design Automation Conference (DAC), 1998, pp. 495-500.
[20] S. Mutoh, S. Shigematsu, Y. Matsuya, H. Fukuda, T. Kaneko, and J. Yamada, "A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application," IEEE J. Solid-State Circuits (JSSC), vol. 31, no. 11, pp. 1795-1802, 1996.
[21] M. Anis, S. Areibi, M. Mahmoud, and M. Elmasry, "Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique," in Proc. IEEE/ACM Design Automation Conference (DAC), 2002, pp. 480-485.
[22] M. Anis, S. Areibi, and M. Elmasry, "Design and optimization of multithreshold CMOS (MTCMOS) circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 10, pp. 1324-1342, 2003.
[23] W. Wang, M. Anis, and S. Areibi, "Fast techniques for standby leakage reduction in MTCMOS circuits," in Proc. IEEE Int. SOC Conference (SOCC), 2004, pp. 21-24.
[24] C. Long and L. He, "Distributed sleep transistor network for power reduction," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 12, no. 9, pp. 937-946, 2004.
[25] E. Pakbaznia and M. Pedram, "Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting," in Proc. Design, Automation and Test in Europe (DATE), 2008, pp. 385-390.
[26] D. S. Chiou, S. H. Chen, and S. C. Chang, "Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 17, no. 9, pp. 1330-1334, 2009.
[27] D. S. Chiou, S. H. Chen, S. C. Chang, and C. W. Yeh, "Timing driven power gating," in Proc. IEEE/ACM Design Automation Conference (DAC), 2006, pp. 121-124.
[28] D. S. Chiou, Y. T. Chen, D. C. Juan, and S. C. Chang, "Sleep Transistor Sizing for Leakage Power Minimization Considering Temporal Correlation," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 8, pp. 1285-1289, 2010.
[29] D. S. Chiou, D. C. Juan, Y. T. Chen, and S. C. Chang, "Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization," in Proc. IEEE/ACM Design Automation Conference (DAC), 2007, pp. 81-86.
[30] C. Neau and K. Roy, "Optimal body bias selection for leakage improvement and process compensation over different technology generations," in Proc. IEEE/ACM Int. Symp. Low Power Electronics and Design (ISLPED), 2003, pp. 116-121.
[31] Y. C. Phong, C. H. Cheng, and J. I. Guo, "Efficient IR drop analysis and alleviation methodologies using dual threshold voltages with gate resizing techniques," in Proc. Int. Conf. Green Circuits and Systems (ICGCS), 2010, pp. 129-132.
[32] J. M. Rabaey, Digital integrated circuits: a design perspective: Prentice Hall, 1996.
[33] B. Razavi, Design of analog CMOS integrated circuits: McGraw-Hill, 2001.
[34] T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE J. Solid-State Circuits (JSSC), vol. 25, no. 2, pp. 584-594, 1990.
[35] C. Prasad, M. Agostinelli, C. Auth, M. Brazier, R. Chau, G. Dewey, T. Ghani, M. Hattendorf, J. Hicks, J. Jopling, J. Kavalieros, R. Kotlyar, M. Kuhn, K. Kuhn, J. Maiz, B. McIntyre, M. Metz, K. Mistry, S. Pae, W. Rachmady, S. Ramey, A. Roskowski, J. Sandford, C. Thomas, C. Wiegand, and J. Wiedemer, "Dielectric breakdown in a 45 nm high-k/metal gate process technology," in Proc. IEEE Int. Reliability Physics Symposium (IRPS), 2008, pp. 667-668.
[36] Synopsys. SMIC-Synopsys Reference Flow 4.0. [Online]. Available: http://www.smics.com/eng/design/reference_flows07.php
[37] Synopsys and E. Wang. Synopsys Power-gating Design Methodology based on SMIC 90nm Process. [Online]. Available: http://www.synopsys.com.cn/information/snug/2007-2008-collection/synopsys-power-gating-design-methodology-based-on-smic-90nm-process
[38] T. Tanzawa and T. Tanaka, "A dynamic analysis of the Dickson charge pump circuit," IEEE J. Solid-State Circuits (JSSC), vol. 32, no. 8, pp. 1231-1240, 1997.
[39] F. Assaderaghi, S. Parke, D. Sinitsky, J. Bokor, P. K. Ko, and H. Chenming, "A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation," IEEE Electron Device Letters (EDL), vol. 15, no. 12, pp. 510-512, 1994.
[40] K. Shimomura, H. Shimano, N. Sakashita, F. Okuda, T. Oashi, Y. Yamaguchi, T. Eimori, M. Inuishi, K. Arimoto, S. Maegawa, Y. Inoue, S. Komori, and K. Kyuma, "A 1-V 46-ns 16-Mb SOI-DRAM with body control technique," IEEE J. Solid-State Circuits (JSSC), vol. 32, no. 11, pp. 1712-1720, 1997.
[41] H. Mostafa, M. Anis, and M. Elmasry, "A Novel Low Area Overhead Direct Adaptive Body Bias (D-ABB) Circuit for Die-to-Die and Within-Die Variations Compensation," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 19, no. 10, pp. 1848-1860, 2011.
[42] M. Barnasconi, "Systemc ams extensions: Solving the need for speed," in Proc. DAC Knowledge center, 2010.
[43] ISCAS Benchmarks. [Online]. Available: http://www.pld.ttu.ee/~maksim/benchmarks/