在本論文中，我們提出了一個針對包含輸入向量錯誤、定值錯誤及橋接錯誤的複數錯誤之具掃描架構與邏輯矩陣的測試晶片。其架構包含了一個二維邏輯單元矩陣與兩組將各邏輯單元塊獨立分隔之掃描鍊組。利用掃描鍊組中之掃描鍊，我們能完全的控制與觀測各邏輯單元塊並提升測試晶片的可測性與診斷能力。我們也提出了一個包含兩組測試的高效診斷流程以診斷該測試晶片上的缺陷。分析結果顯示我們的診斷流程在單一錯誤的情況下皆能達到100%的準確率。當考慮包含0、1或2個橋接錯誤之雙重錯誤，我們的診斷流程能分別在99.38%、98.398%與97.416%的情況下達到100%的準確度並能分別在98.81%、98.006%與97.202%的情況下達到完美的診斷解析度。另外，當錯誤不存在於掃描暫存器內時，無論有多少錯誤存在，我們的診斷流程皆能回報所有包含錯誤的邏輯單元塊。

In this thesis, we proposed a scan-based test chip architecture targeting the diagnosis of multiple faults consisting of input pattern faults, stuck-at faults and bridging faults. The architecture consists of a two-dimensional array of logic blocks and two sets of scan chains isolating the logic blocks. The scan chains are used to fully control and observe the logic blocks so as to enhance the testability and diagnosability of test chips. An efficient diagnostic procedure composed of two tests is developed to carry out the defect diagnosis process. Evaluation results show that our proposed procedure can always achieve 100% accuracy for single faults. When double faults containing 0, 1, and 2 bridging faults are considered, our proposed procedure can achieve 100% accuracy for 99.38%, 98.398%, and 97.416% of the faults and achieve perfect resolution for 98.81%, 98.006%, and 97.202% of the faults, respectively. Moreover, no matter how many faults exist, as long as no fault affects the scan registers, the proposed procedure can report all faulty logic blocks.

[1] L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability, Morgan Kaufmann, 2006.
[2] R. Guo, L. Lai, Y. Huang and W. T. Cheng, “Detection and Diagnosis of Static Scan Cell Internal Defect,” in Proc. IEEE Int. Test Conf., 2008, pp. 1-10.
[3] K. Wang and S. Y. Kuo, “Fault detection and location in reconfigurable VLSI arrays,” in Proc. IEEE Int. Conf. Comput.-Aided Des. Digest of Technical Papers, 1989, pp. 234-237.
[4] J. C. Lien and M. A. Breuer, “Maximal Diagnosis for Wiring Networks,” in Proc. Int. Test Conf., 1991, pp. 96-.
[5] S. L. Lin, C. H. Wu, and K. J. Lee, “Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis” in Proc. IEEE 25th Asian Test Symp., 2016, pp. 25-30.
[6] C. Hess, B. E. Stine, and L. H. Weiland, “Logic Characterization Vehicle to Determine Process Variation Impact on Yield and Performance of Digital Circuits,” in Proc. Int. Conf. on Microelectronic Test Structures, 2002, pp. 189-196.
[7] Y. Huang and W. T. Cheng, “On Designing Two-Dimensional Scan Architecture for Test Chips” 2017 Int. Symp. on VLSI Design, Automation and Test, 2017, pp. 1-4.
[8] R. D. Blanton, B. Niewenhuis, and C. Taylor, “Logic Characterization Vehicle Design for Maximal Information Extraction for Yield Learning”, in Proc. IEEE Int. Test Conf., 2014, pp. 1-10.
[9] R. D. Blanton, B. Niewenhuis and Z. Liu, “Design Reflection for Optimal Test-Chip Implementation” in Proc. IEEE Int. Test Conf., 2015, pp. 1-10.
[10] L. M. Huisman “Diagnosing Arbitrary Defects in Logic Designs Using Single Location at a Time (SLAT)”, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 23, no. 1, pp. 91-101, Jan. 2004.
[11] S.-M. Chao, P.-J. Chen, J.-Y. Chen and et al., “Divide and Conquer Diagnosis for Multiple Defects”, in Proc. Int. Test Conf., 2014, pp. 1-8.
[12] X. Yu, and R. D. Blanton, “Diagnosis of Integrated Circuits With Multiple Defects of Arbitrary Characteristics”, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 29, no. 6, pp. 977-987, June 2010.
[13] B. Niewenhuis, S. Mittal and R. D. Blanton, “Multiple-Defect Diagnosis for Logic Characterization Vehicles”, in Proc. IEEE European Test Symp., 2017, pp. 1-6.
[14] A. D. Friedman, “Easily Testable Iterative Systems”, IEEE Trans. on Computers, vol. C-22, no. 12, pp. 1061-1064, Dec. 1973.
[15] C. W. Wu and P. R. Cappello, “Easily Testable Iterative Logic Arrays”, IEEE Trans. on Computers, vol. 39, no. 5, pp. 640-652, May 1990.
[16] R. D. Blanton and J. P. Hayes, “Properties of The Input Pattern Fault Model”, in Proc. Int. Conf. on Computer Design VLSI in Computers and Processors, 1997, pp. 372-380.
[17] R. Guo and S. Venkataraman, “A Technique for Fault Diagnosis of Defects in Scan Chains”, in Proc. Int. Test Conf., 2001, pp. 268-277.
[18] Synopsys, Inc., TetraMAX ATPG User Guide, Version J-2014.09-SP1, 2014.