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研究生: 郭姿吟
Kuo, Tzu-Yin
論文名稱: 適用於雲端運算之高效同態AES硬體架構設計
High Performance Hardware Architecture Design of Homomorphic AES for Cloud Computing
指導教授: 謝明得
Shieh, Ming-Der
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2017
畢業學年度: 105
語文別: 英文
論文頁數: 73
中文關鍵詞: 全同態加密同態AESVLSI架構
外文關鍵詞: Fully Homomorphic Encryption (FHE), Homomorphic Advanced Encryption Standard (AES), VLSI Architecture
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  • 全同態加密(Fully homomorphic encryption, FHE)是一個新興的加密技術,能在第三方的伺服器中直接對加密的資料進行運算以確保原始資料的隱密性。儘管全同態加密技術在雲端運算的應用中占有極大的重要性,以目前提出的演算法來實現仍需非常高的計算複雜度和硬體成本。同態AES可視為一個複雜的運算函數,現今被提出的同態AES方案皆需龐大的計算時間,其中最花時間的部分是金鑰交換(key-switching)運算,在每一次同態乘法運算、自同構(automorphism)運算後皆會需要進行金鑰交換運算。
    本論文提出平行化的SubByte和MixColumn/ShiftRow演算法,主要是透過在關鍵運算路徑上降低同態乘法運算和自同構運算的資料相依性,使其在高平行度的程序下運算能減少同態AES的運算時間。在平行處理下,相較於傳統的同態AES演算法,所提出的演算法可以使同態AES一回合中減少3次金鑰交換運算時間。此外,本論文也基於不同的安全性考量下,提出各個高效能的同態AES硬體架構, 所提出的硬體架構相較於現有的同態AES方案上有著較少的運算時間及更高的效能。

    Fully homomorphic encryption (FHE) is an emerging technique that allows the encrypted data to be processed directly in untrusted servers for ensuring data privacy. Despite of the important feature of FHE in cloud computing applications, there are still extremely high computation complexity and implementation cost in the underlying algorithms. Homomorphic evaluation of advanced encryption standard (AES) can be regarded as a complex function, in which existing homomorphic AES implementations still demand a significant amount of computational time. The most expensive operation in homomorphic AES is key switching after homomorphic multiplication and automorphism operations.
    To improve the performance of homomorphic AES by reducing homomorphic multiplication and automorphism operations in critical computational paths, this thesis proposes a parallel SubByte and MixColumn/ShiftRow algorithm by relaxing the underlying data dependency. Compared to the conventional homomorphic AES, the proposed one can reduce 3 key switching operations in one round of homomorphic AES assuming parallel processing. Moreover, high-performance hardware architectures of homomorphic AES are presented for different security levels. Performance evaluations show that the proposed design outperforms the related works in terms of computational time and performance.

    摘   要 i ABSTRACT iii 致謝 v Content vi List of Tables viii List of Figures ix Chapter 1. Introduction 1 1.1 Motivation 1 1.2 Thesis organization 4 Chapter 2. Background 5 2.1 Fully homomorphic encryption 5 2.2 Ring-learning with error based BGV fully homomorphic encryption scheme 6 2.2.1 BGV-FHE scheme 7 2.2.2 Modulus switching 9 2.2.3 Key-switching 9 2.3 Aggregate plaintext 11 2.4 DoubleCRT 15 2.5 Homomorphic AES algorithm 17 2.5.1 AddRoundKey algorithm 17 2.5.2 SubByte algorithm 18 2.5.3 MixColumn/ShiftRow algorithm 20 2.6 Time profiling 21 Chapter 3. Proposed homomorphic AES parallel algorithm 22 3.1 SubByte parallel algorithm 22 3.2 MixColumn/ShiftRow parallel algorithm 26 3.3 Time complexity analysis assuming parallel processing 33 Chapter 4. Hardware design of homomorphic AES 38 4.1 Homomorphic AES architecture 38 4.2 Key-switching architecture 40 4.2.1 Scale unit design 40 4.2.2 Two key-switching design 58 4.3 Performance evaluation 61 4.3.1 Area analysis 61 4.3.2 Timing analysis 63 4.4 Comparison 67 Chapter 5. Conclusion and future Work 69 5.1 Conclusion 69 5.2 Future work 70 References 71

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