在諸如高解析度電視、數位相機、通訊與醫療影像系統等數位影像技術的應用方面，常需要不同的系統架構與電路來進行訊號的處理。而在這些系統與電路裡，取樣頻率達100Mhz~200Mhz，解析度要求8位元~12位元的類比數位轉換器在類比訊號處理中，會是關鍵的元件。本論文所敘述的是用於視訊應用的1.8伏特十位元每秒135百萬次取樣速率類比數位轉換器。此類比數位轉換器採取二階式的架構，其電路主要被分成兩個部份:六位元的粗調類比數位轉換器與五位元的類比數位轉換器。此二階式類比數位轉換器在微調類比數位轉換器的運作上採取時間分離式的方式，而在135Mhz的取樣頻率，25.18066406Mhz的輸入弦波訊號情況下，可達到9.217位元的解析度。本類比數位轉換器是採用TSMC 1P6M 0.18um的CMOS製程，而整體晶片在1.8V電源供應下的功率消耗為108mW，而包括pad在內的面積需求為1.8*2.3mm2。

　Digital video applications, such as HDTV, digital camera, communication, and medical imaging system require various system architectures and circuits for signal processing. Among these, A/D converters are key components in analog signal processing, and require conversion speed 100MS/s ~ 200MS/s, resolution 8~12 bit. This thesis describes a 1.8V, 10-bit, 135MS/s A/D converter suitable for video applications. The proposed A/D converter is designed with a two-step architecture and is divided into two primary components, a 6-bit coarse converter and a 5-bit fine converter. The two-step ADC with interleaved fine conversions achieves 9.217bits with a sampling frequency of 135Mhz and a sinusoidal input signal of 25.18066406MHz frequency simulation. The A/D converter is implemented with TSMC 1P6M 0.18um mixed-signal process. The chip power consumption is 108mW at 1.8V power supply and area including pads is 1.8*2.3mm2.

[1] G. E. Moore, “Cramming more components onto integrated circuits,” Electronics, vol. 38, no. 8, April 1965.
[2] W. H. Wolf, Modern VLSI Design: Systems on Silicon, 2nd ed., New Jersey: Prentice Hall, 1998.
[3] R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing, New York: John Wiley & Sons, 1986.
[4] W. Kester, “High Speed Sampling and High Speed ADCs,” in High Speed Design Techniques, W. Kester, Ed. Norwood, MA: Analog Devices, Inc., 1996.
[5] H. D. Lüke, Signalübertragung: Grundlagen der digitalen und analogen Nachrichtenübertragungssysteme, 5th ed., Berlin, BRD: Springer-Verlag, 1992.
[6] R. Harjani, “Data Converters: Analog-to-Digital Converters,” in The Circuits and Filters Handbook, The Electrical Engineering Handbook Series, W.-K. Chen, Ed. New York: CRC Press, Inc., 1995.
[7] K.-L. Lin, Entwicklung von Schaltungstechniken zur Fehlerreduzierung in monolithischen Folding-Analog/Digital-Umsetzern, Dipl.-Ing. thesis, Duisburg: Gerhard-Mercator-Universität Duisburg, 1998.
[8] I. N. Bronstein and K. A. Semendjajew, Taschenbuch der Mathematik, 25th ed., Stuttgart, BRD: B. G. Teubner Verlagsgesellschaft, 1991.
[9] W. Kaplan, Advanced Mathematics for Engineers, Reading, MA: Addison-Wesley, 1981.
[10] R. J. v. d. Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters, Boston: Kluwer Academic, 1994.
[11] IEEE, IEEE Standard 1241 Draft: Standard for Terminology and Test Methods for Analog-to-Digital Converters, Piscataway, NJ: IEEE, 2000.
[12] D. Seitzer, G. Pretzl, and N. A. Hamdy, Electronic analog-to-digital converters, Chichester: John Wiley & Sons Ltd., 1983.
[13] L. Gaddy, “Application Bulletin: Selecting an A/D Converter,” Burr-Brown Corp., Tucson, AZ, Application Bulletin AB-098, 1995.
[14] D. F. Hoeschele, Analog-to-Digital and Digital-to-Analog Conversion Techniques, 2nd ed., New York: John Wiley & Sons, 1994.
[15] W. Kester, “High Speed A/D Conversion,” in High Speed Design Seminar, W. Kester, Ed. Norwood, MA: Analog Devices, Inc., 1990.
[16] R. J. v. d. Plassche, “Introduction to High-Speed A/D and D/A Converters,” in Advanced Engineering Course on High-Speed Data Converters. Lausanne, Switzerland: École Polytechnique Fédérale de Lausanne, 1998.
[17] R. J. v. d. Plassche, “Practical Examples of High-Speed A/D and D/A Conversion in Sub-Micron CMOS,” in Advanced Engineering Course on High-Speed Data Converters. Lausanne, Switzerland: École Polytechnique Fédérale de Lausanne, 1998.
[18] M. Choi and A. A. Abidi, “A 6 b 1.3 GSample/s A/D converter in 0.35 mu m CMOS,” in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2001.
[19] G. Geelen, “A 6 b 1.1 GSample/s CMOS A/D converter,” in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2001.
[20] S. Gotoh, T. Takahashi, K. Irie, K. Ohshima, N. Mimura, K. Aida, T. Maeda, T. Yamamoto, K. Sushihara, Y. Okamoto, Y. Tai, T. Nakajima, M. Usui, T. Ochi, K. Komichi, and A. Matsuzawa, “A mixed-signal 0.18 mu m CMOS SOC for DVD systems with 432 MS/s PRML read channel and 16 Mb embedded DRAM,” in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2001.
[21] H. v. d. Ploeg, G. Hoogzaad, H. A. H. Termeer, M. Vertregt, and R. L. J. Roovers, “A 2.5 V 12 b 54 MSample/s 0.25 mu m CMOS ADC in 1 mm/sup 2,” in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2001.
[22] R. C. Taft and M. R. Tursi, “A 100-MS/s 8-b CMOS subranging ADC with sustained parametric performance from 3.8 V down to 2.2 V,” IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 331-338, March 2001.
[23] L. Singer, “High-Speed Pipelined ADC Architectures,” in Advanced Engineering Course on High-Speed Data Converters. Lausanne, Switzerland, 1998.
[24] H.-S. Chen, B.-S. Song, and K. Bacrania, “A 14-b 20-Msamples/s CMOS pipelined ADC,” IEEE Journal of Solid-State Circuits, vol. 36, no. 6, pp. 997-1001, June 2001.
[25] A. Gerosa, R. Bernardini, and S. Pietri, “A fully integrated 8-bit, 20 MHz, truly random numbers generator, based on a chaotic system,” in Southwest Symposium on Mixed-Signal Design, Austin, TX, 2001.
[26] H. Liu and M. Hassoun, “High speed re-configurable pipeline ADC cell design,” in Southwest Symposium on Mixed-Signal Design, Austin, TX, 2001.
[27] D. Miyazaki and S. Kawahito, A high-speed low-power area-efficient pipeline A/D converter and its design method, Report, Hamamatsu, Japan: Shizuoka University, 2001.
[28] B. Nejaati, A. Khakifirooz, S. J. Ashtiani, and O. Shoaei, “Pipeline analog-to-digital converters with radix <2,” in The 12th International Conference on Microelectronics (ICM), Tehran, Iran, 2000.
[29] Y.-I. Park, S. Karthikeyan, F. Tsay, and E. Bartolome, “A 10 b 100 MSample/s CMOS pipelined ADC with 1.8 V power supply,” in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2001.
[30] P. P. Siniscalchi, J. K. Pitz, R. K. Hester, S. M. DeSoto, W. Minsheng, S. Sridharan, R. L. Halbach, D. Richardson, W. Bright, M. M. Sarraj, J. R. Hellums, C. L. Betty, and G. Westphal, “A CMOS ADSL codec for central office applications,” IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 356-365, March 2001.
[31] M. Waltari and K. A. I. Halonen, “1-V 9-bit pipelined switched-opamp ADC,” IEEE Journal of Solid-State Circuits, vol. 36, no. 1, pp. 129-134, January 2001.
[32] H. Pan, M. Segami, M. Choi, L. Cao, and A. A. Abidi, “A 3.3-V 12-b 50-MS/s A/D converter in 0.6- mu m CMOS with over 80-dB SFDR,” IEEE Journal of Solid-State Circuits, vol. 35, no. 12, pp. 1769-1780, December 2000.
[33] C. Shi, Y. Wu, C.-H. Lin, S. Li, and M. Ismail, “Design and power optimization of high-speed pipeline ADC for wideband CDMA applications,” in The 17th NORCHIP Conference, Oslo, Norway, 1999.
[34] H. Bilhan and M. W. Gosney, “A 13 bit 20 MS/s current mode pipelined analog to digital converter,” in The 42nd Midwest Symposium on Circuits and Systems, Las Cruces, NM, 1999.
[35] S. Imai and Y. Sugimoto, “A design of a bit-block circuit applicable to a 1 V operational video-rate current-mode CMOS A/D converter,” Transactions of the Institute of Electrical Engineers of Japan, Part C, vol. 120-C, no. 10, pp. 1325-1332, October 2000.
[36] D. G. Nairn, “A 10-bit, 3 V, 100 MS/s pipelined ADC,” in IEEE Custom Integrated Circuits Conference (CICC), Orlando, FL, 2000.
[37] I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC,” IEEE Journal of Solid-State Circuits, vol. 35, no. 3, pp. 318-325, March 2000.
[38] I. Galton, “Digital cancellation of D/A converter noise in pipelined A/D converters,” IEEE Transactions on Circuits & Systems II-Analog & Digital Signal Processing, vol. 47, no. 3, pp. 185-196, March 2000.
[39] D. Kelly, W. Yang, I. Mehr, M. Sayuk, and L. Singer, “A 3 V 340 mW 14 b 75 MSPS CMOS ADC with 85 dB SFDR at Nyquist,” in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2001.
[40] B. Razavi, “Folding and Interpolating ADCs,” in Advanced Engineering Course on High-Speed Data Converters. Lausanne, Switzerland: École Polytechnique Fédérale de Lausanne, 1998.
[41] W. T. Colleran and A. A. Abidi, “A 10-b, 75-MHz two-stage pipelined bipolar A/D converter,” IEEE Journal of Solid-State Circuits, vol. 28, no. 12, pp. 1187-1199, December 1993.
[42] R. E. J. v. d. Grift and R. J. v. d. Plassche, “A monolithic 8-bit video A/D converter,” in 9th European Solid-State Circuits Conference (ESSCIRC), Lausanne, Switzerland, 1983.
[43] R. E. J. v. d. Grift and R. J. v. d. Plassche, “A monolithic 8-bit video A/D converter,” IEEE Journal of Solid-State Circuits, vol. SC-19, no. 3, pp. 274-278, June 1984.
[44] R. E. J. v. d. Grift, I. W. J. M. Rutten, and M. v. d. Veen, “An 8-bit video ADC incorporating folding and interpolation techniques,” IEEE Journal of Solid-State Circuits, vol. SC-22, no. 6, pp. 944-953, December 1987.
[45] R. J. v. d. Plassche and P. Baltus, “An 8-bit 100-MHz full-Nyquist analog-to-digital converter,” IEEE Journal of Solid-State Circuits, vol. 23, no. 6, pp. 1334-1344, December 1988.
[46] J. v. Valburg and R. J. v. d. Plassche, “An 8-b 650-MHz folding ADC,” IEEE Journal of Solid-State Circuits, vol. 27, no. 12, pp. 1662-1666, December 1992.
[47] M. P. Flynn and D. J. Allstot, “CMOS folding ADCs with current-mode interpolation,” in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 1995.
[48] K. L. Lin, T. van den Boom, N. Stevanović, J. Driesen, D. Hammerschmidt, and B. Hosticka, “A basic design guide for CMOS folding and interpolating A/D converters-overview and case study,” in The 6th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Pafos, Cyprus, 1999.
[49] K.-M. Kim and K.-S. Yoon, “An 8-bit 42 Msamples/s current-mode folding and interpolation CMOS analog-to-digital converter with three-level folding amplifiers,” in The 39th Midwest Symposium on Circuits and Systems, Ames, IA, 1996.
[50] K.-M. Kim and K.-S. Yoon, “An 8-bit CMOS current-mode folding and interpolation A/D converter with three-level folding amplifiers,” in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Seoul, South Korea, 1996.
[51] M. P. Flynn and B. Sheahan, “A 400-Msample/s, 6-b CMOS folding and interpolating ADC,” IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 1932-1938, December 1998.
[52] M. Flynn and B. Sheahan, “A 400 M sample/s 6b CMOS folding and interpolating ADC,” in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 1998.
[53] X. Jiang, Y. Wang, and A. N. Willson, Jr., “A 200 MHz 6-bit folding and interpolating ADC in 0.5-mu m CMOS,” in IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, 1998.
[54] K.-M. Kim and K.-S. Yoon, “An 8 bit current-mode CMOS A/D converter with three level folding amplifiers,” IEICE Transactions on Fundamentals of Electronics Communications & Computer Sciences, vol. E81-A, no. 2, pp. 252-255, February 1998.
[55] H.-H. Kim and K.-S. Yoon, “A 12 bit current-mode folding/interpolation CMOS A/D converter with multipliers,” in IEEE Region 10 Conference (TENCON 99) 'Multimedia Technology for Asia-Pacific Information Infrastructure', Cheju Island, South Korea, 1999.
[56] K.-M. Kim and K. S. Yoon, “An 8 bit current-mode CMOS A/D converter with three level folding amplifiers,” Analog Integrated Circuits & Signal Processing, vol. 20, no. 2, pp. 139-143, August 1999.
[57] M.-J. Choe, B.-S. Song, and K. Bacrania, “An 8 b 100 MSample/s CMOS pipelined folding ADC,” in Symposium on VLSI Circuits, Kyoto, Japan, 1999.
[58] H.-H. Kim and K.-S. Yoon, “A 12 bit current-mode folding/interpolation CMOS A/D converter with 2 step architecture,” in The 1st IEEE Asia Pacific Conference on ASICs (AP-ASIC), Seoul, South Korea, 1999.
[59] M. Gustavsson, J. Jacob Wikner and Nianxiong Nick Tan, CMOS Data Converters for Communications, Kluwer Academic Publishers, ISBN: 0-7923-7780-X, 2000.
[60] David A. Johns and Ken Martin, Analog Integrated Circuit Design, John Wiley and Sons, ISBN:0-471-14448-7, 1997.
[61] A. R. Bugeja and B. S. Song, “A Self-Trimming 14-b 100MS/s CMOS DAC,” IEEE Journal of Solid-State Circuits, vol. 35, pp.1841-1852, Dec. 2000.
[62] D. Groeneveld, et al., “A Self-Calibration Technique for Monolithic High Resolution D/A Converters,” IEEE Journal of Solid-State Circuits, vol. 24, pp.1517-1522, Dec. 1989.
[63] I. Galton, “Spectral Shaping of Circuit Errors in Digital-to-Analog Converters,” IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 44, no. 10, pp. 808-817, Oct. 1997.
[64] H. T. Jensen and I. Galton, “A Low-Complexity Dynamic Element Matching DAC for Direct Digital Synthesis,” IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, no. 1, pp. 13-27, Jan. 1998.
[65] P. K. Henderson and O. J. A. P. Nys, “Dynamic Element Matching Techniques with Arbitrary Noise Shaping Function,” International Symposium on Circuit and Systems, vol. 1, pp. 293-296, 1996.
[66] Y. H. Lin, D. H. Lee, C. C. Yang and T. H. Kuo, “High-Speed DACs with Random Multiple Data-Weighted Averaging Algorithm, ” IEEE International Symposium on Circuits and Systems, vol. 1, pp. 993-996, May 2003.
[67] Z. Yu, D. Chen and R. Geiger, “1-D and 2-D Switching Strategies Achieving Near Optimal INL for Thermometer-Coded Current Steering DACs,” IEEE International Symposium on Circuits and Systems, vol. 1, pp. 909-912, May 2003.
[68] A. van den Bosch, M. Steyaert, and W. Sansen, “SFDR-Bandwidth Limitations for High-Speed High-Resolution Current-steering CMOS D/A Converters,” International Conference on Electronics, Circuits and Systems, pp. 1193–1196, Sept. 1999.
[69] A. van den Bosch, M. Borremans, M. Steyaert, and W. Sansen, “A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter,” Custom Integrated Circuits Conference, pp. 265-268, May 2000.
[70] Y. Yoo and M. Song, “Design of a 1.8V 10bit 300MSPS CMOS Digital-to-Analog Converter with a Novel Deglitching Circuit and Inverse Thermometer Decoder,” Asia-Pacific Conference on Circuits and Systems, vol. 2, pp. 311-314, Oct. 2002.
[71] Keh-La Lin, Armin Kemna, and Bedrich J. Hosticka, Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems, MA: Kluwer Academic Publishers, Boston, ISBN: 1-4020-7380-1, pp. 254, April 2003.