隨著半導體製程之演進，晶片將擁有越來越多的功能。然而以系統單晶片為基礎之設計方法面臨許多挑戰。為了有效測試系統單晶片，以測試機台為基礎之測試方法將需要擁有極高頻率、高精準度以及大量記憶體配置之測試機台。如此將會使測試成本大幅提升。此外由於系統單晶片複雜度之增長，過長之測試時間亦為一極待解決之問題。這將會造成測試成本的提升，因此，如何針對系統單晶片降低其測試成本將是個非常重要之課題。
　　為了解決這些問題，在此篇論文裡，我們提出具有混合信號測試能力之單晶片系統測試平台之高效能元件設計，可同時支援掃描練測試、記憶體內建自我測試與類比數位轉換器之內建自我測試。此高性能元件包含高性能測試控制器與階層式測試匯流排，測試控制器可在300MHz達到「即時」測試（At speed testing）之需求。而階層式測試匯流排之技術，使本單晶片系統測試平台可應用於內部核心與模組數量與種類之迅速增長之單晶片系統而不會造成晶片操作速度之下降。根據實驗結果顯示，藉由使用我們所提出之技術，單晶片系統測試平台之功能性可以大幅度的提升。

　　With the development of process of semi-conductor, more and more functionalities will be provided in a single chip. However, the SOC-based design methodology also introduces many new challenges. In order to test an SOC, the ATE-based testing methodology requires ATE with high frequency, great accuracy and large memory. This ATE will result in high test cost. Moreover, with the increase of SOC complexity, the possibly long test time will also be an important issue. Hence, how to reduce the test cost for SOC becomes an important problem.
　　In order to address the problems above, in this thesis, we propose the high-performance components for SOC which has high operation speed and supports various types of test methodologies including scan-based testing, memory BIST and ADC BIST. These components contain a high-performance test controller and the test bus. The improved test controller has the ability of 300MHz at-speed testing. As for the test bus, we develop a hierarchical test bus technique. With the aid of this technique, the SOC test platform can support testing of a large number of cores without performance degradation. Experimental results show that by using the proposed techniques, the SOC test platform can be greatly improved.

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