近年來，因為成熟的製程與低製作成本，非晶矽技術已經被廣泛的應用在主動式液晶顯示器上，而為了有效的提升畫面品質，半穿反式液晶顯示器已經被提出且廣泛的應用在多種可攜式的產品上，除此之外，為降低面板的成本，主動式液晶顯示器之驅動電路採用薄膜電晶體技術且設計在面板上已逐漸成為主流的趨勢。然而非晶矽薄膜電晶體元件會因為長時間的使用或者是高偏壓施加而產生臨界電壓的漂移，進而影響到驅動電路的穩定度，導致畫面的顯示品質下降。
本論文首先即針對設計可應用於半穿反式液晶顯示器之畫素電路，其電路架構採用傳統的二顆非晶矽薄膜電晶體與兩顆儲存電容，只需要一條資料線來提供所需的電壓值，可有效的改善面板開口率與減少電路額外的製作成本。從模擬結果可以了解本次所提出之電路有完整的匹配穿透區所需要的儲存電壓且在中低灰階下可以有效的儲存反射區所需要的儲存電壓，除此之外，當薄膜電晶體之臨界電壓改變0.3 V與漂移率改變± 5 %時，本次所提出之電路在誤差比中可以被抑制在3 %以下。第二與第三個電路則是提出新式非晶矽閘極驅動電路，且透過電路模擬軟體以及實驗結果驗證其電路之有效性。第二個電路由十三顆非晶矽薄膜電晶體、兩顆電容與四組訊號線所組成，並藉由額外增加四顆薄膜電晶體來使電路可操作在雙向傳輸之功能。此電路結合交流式電流驅動方法來減緩電路中非晶矽薄膜電晶體臨界電壓漂移的現象，同時抑制輸出電壓產生浮動的現象。實驗結果顯示在100 ℃下，此電路能穩定操作超過240小時，且輸出端充、放電達穩態所需時間分別為6.6 μs和5.5 μs。第三個電路是採用十二顆非晶矽薄膜電晶體、一顆電容與六組訊號線的架構。此電路利用兩組低頻率交替式下拉電路來穩定輸出波形且降低消耗功率，並藉由反向偏壓來改善電路中非晶矽薄膜電晶體臨界電壓漂移的現象。實驗結果顯示在100 ℃下，此電路能穩定操作超過240小時，輸出端充、放電達穩態所需時間分別為7.8 μs和5 μs，功率消耗在與之前所提出的閘極驅動電路相比可改善52.6 %。

Hydrogenated amorphous silicon technology is widely used in active-matrix LCD (AMLCD) panels due to its mature manufacturing capabilities and reduced overhead costs in recent years. Efforts to improve the display quality have led to increasing market demand for transflective liquid crystal displays (LCDs) for portable products due to their excellent merits of thinness, lightweight and low power consumption. Additionally, further reducing overhead costs has led to the popularity of active matrix liquid crystal displays (AM-LCDs) that utilize thin film transistors (TFTs) as a switching component for the gate driver circuit. However, the threshold voltage shift of hydrogenated amorphous silicon (a-Si:H) TFTs due to long-term operation or high-bias stress deteriorates the stability of a gate driver circuit, ultimately lowering the image quality of the AM-LCDs.
This dissertation proposes a novel single-cell-gap transflective liquid crystal display with two thin-film-transistors, two capacitors, and only one data line. The proposed circuit can increase the aperture ratio and reduce the fabrication costs. Simulation results indicate that the stored voltages closely correspond to the required data voltages in the T region and close to the low and middle gray levels in the R region. Moreover, the estimated maximum deviation of the stored voltage is less than 3 % in the T-mode and R-mode, while △VTH of TFTs is 0.3 V and the mobility variation of TFTs is ± 5 %, respectively. Two novel gate driver circuits are then developed, with experimental and simulation results verifying their feasibility. The first gate driver circuit, composed of 13 a-Si:H TFTs, two capacitors and 4 clock signals, utilizes an AC-driving structure in the proposed circuit to suppress the VTH shift of TFTs and prevent the row line from floating. Experimental results indicate that this circuit can operate stably for more than 240 hours at 100 ℃. The rising time (TRISE) and falling time (TFALL) of the output voltage in the first circuit are 6.5 μs and 5.5 μs, respectively. The second gate driver circuit, consisting of 12 a-Si:H TFTs, 1 capacitor and 6 clock signals, uses two low frequency alternative pull-down circuits to stabilize the output waveform and reduce the power consumption. Experimental results indicate that this circuit can operate stably for more than 240 hours at 100 ℃. The rising time (TRISE) and falling time (TFALL) of the output voltage are 7.8 μs and 5 μs, respectively. Additionally, according to the measurement results, the second gate driver circuit achieves a 52.6 % low power consumption than that of previous circuits.

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