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研究生：	蕭宇宏 Shiau, Yeu-Horng
論文名稱：	應用階層式設計方法之小波視訊編碼晶片設計 Design of a Wavelet-based Video Codec with a Hierarchical Methodology
指導教授：	周哲民 Jou, Jer Min
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	256
中文關鍵詞：	視訊編解碼系統、小波轉換
外文關鍵詞：	video codec, wavelet transform
相關次數：	點閱：53 下載：2
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　　近年來多媒體系統的相關產品與服務不斷推陳出新，為了要將多媒體的大量資料在有限的網路頻寬上傳輸以及儲存資料，高效能的資料壓縮方法之研發，變得愈來愈重要。目前已有許多視訊的標準編碼法被制定，例如: JPEG、MPEG、以及H.263等，這些編碼法包含許多的壓縮技術，例如：轉換編碼法、變動長度編碼法、以及移動向量估計與補償法。這些編碼法通常包含很多的數學運算，為了達到即時處理的應用，以硬體實現這些演算法將是十分重要的課題。一般而言，處理多媒體資料的演算法含有大量且多層的迴圈，為了要達到高效能的硬體架構，本篇論文首先提出一個階層式設計方法，用於階層式管線化系統的行為，發展高效能的硬體架構。這各階層式設計方法包含三個模型用來漸進式的完成系統硬體架構，三個模型分別是：階層式行為模型、虛擬元件模型、以及狀態轉移模型。
　　接著本文介紹我們所發展的小波轉換(discrete wavelet transform, DWT)視訊編解碼系統，其中結合了小波影像壓縮技術以及移動向量估計與補償法。這個編碼法十分類似傳統餘弦轉換(discrete cosine transform, DCT)視訊編碼法，不同的是小波轉換視訊編碼法利用DWT替代DCT，同時採用JPEG2000標準中的EBCOT(Embedded Block Coding with Op-timized Truncation)熵編碼法壓縮小波轉換後的係數。而在消除畫面間時間累贅方面，我們使用之前所提出的灰色向量估計法(GrPS)作為移動向量估計演算法(motion estimation, ME)來加快搜尋速度，實驗數據顯示GrPS在各方面的總合皆優於其他的搜尋演算法。接下來，為了達到即時處理的應用，藉由上述的階層式設計方法將發展的小波視訊編碼法分成幾個主要的模組設計其高效能的硬體架構，這些模組分別是: DWT模組、EBCOT模組、以及ME模組。
　　在小波模組的設計方面，我們針對正交二維小波正轉換提出一個摺疊式管線化架構，另外，針對正交二維小波反轉換提出一個樹狀方塊管線化架構，這兩種架構皆能降低儲存空間以及加速運算效能。而針對雙正交小波正反轉換提出高效能管線化架構，在一個時脈可以同時處理兩筆資料，並且同一個架構可以執行正轉換與反轉換的運算。實現數據顯示提出的架構可以應用在即時處理的系統上。在EBCOT模組設計方面，我們設計與實現一個高效能的硬體架構。 EBCOT主要分成兩個部分: context產生器以及MQ算數編碼。我們採用一個有效率的記憶體配置模式應用在context產生器中，使得讀取記憶體所需的時間為原來的1/4。在MQ算數編碼中，我們使用變動潛伏期(latency)的管線化方式加速運算的時間，實驗數據顯示經過此特殊管線化方法可以提升將近一倍的運算速度。因此適合用於即時處理的系統上。在ME模組設計方面，我們應用灰色預測來設計一個快速的灰色預測搜尋(GrPS)法，並提出實現此法的VLSI架構。此GrPS晶片包含大約54K個電晶體，面積為，能即時處理MPEG規格的影像。

　Recently, multimedia systems have become very popular. The fundamental characteristic of multimedia systems is that they incorporate continuous media, such as voice, fullmotion video, and graphics. To transmit these multimedia data through band-limited networks or for storage purpose, compression algorithms are needed to compress tremen-dous original visual information into more compact formats. Up to now, there have been many successful researches and standards for the compression of image and video signals, such as JPEG, MPEG, and H.263. The video coding standard inducted several compression techniques, such as transfer coding, variable-length coding (VLC), and motion estimation and compensation. The video coding system is a time-critical digital system. In order to meet the required real-time performance, the hardware implementation of video coding system becomes an important task. Generally, behavioral specifications of multimedia and/or digital signal processing systems contain a number of nested loops. To obtain high data rates for such systems, it is necessary to pipeline the behavior blocks, the loop bodies, and also the operations. In order to hierarchically pipeline a performance-constrained system, to develop a hierarchical system design methodology to shorten design and verification time becomes more and more important in high performance multimedia system designs.
　In this dissertation, we focus on the video coding system and the technologies adopted in them. We proposed a DWT-based video coding system which combined the DWT im-age compression and the motion estimation and compensation techniques. The system has very similar architecture as the traditional hybrid DCT video coding systems, like MPEG or H.263. The difference is that the DCT is replaced by the DWT, and since the basically different properties of the DWT from the DCT, such that the tree-like structure property and self-similarity between wavelet coefficients of different subbands, the following entropy coding algorithm for DCT coefficients may need to be changed for better compres-sion rate. In the proposed architecture, we adopted the MQ arithmetic coding, which is the technique used in JPEG2000 standard, as the entropy coding algorithm.
　In order to design and implement the DWT-based video coding system, we develop a hierarchical system design methodology for propagating constraints and hierarchically pipelining a performance-constrained system. The methodology is a synthesis-based approach where the three abstraction models: the hierarchical specification model, the virtual component model, and the super-state transition model, are adopted for gradually refining the define specification into the implementation. Adopting the hierarchical system design methodology, the DWT-based video coding system is partitioned into several core modules, the motion estimation (ME) module, the discrete wavelet transform (DWT) module, the inverse discrete wavelet transform (IDWT) module, and the embedded block coding with optimized truncation (EBCOT) module. In this dissertation, we design and implement these main core modules to meet the requirement for the real-time applications.
　In the design of the DWT, we proposed several 2-D DWT and IDWT architectures for orthogonal and biorthogonal wavelet systems. According to the results of our comparison, our architectures prove to be better than other existing architectures in the hardware cost and latency requirements. Because of its small storage size, regularity, and high performance, the architectures are suited to time-critical applications, such as MPEG-4 and JPEG-2000.
In the design of the EBCOT, we design and implement a high performance architecture of the EBCOT. The EBCOT is divided into two parts, the context information generator and the MQ arithmetic coder. The context information generator adopted efficient memory architectures both in the state variable memory and the code block memory to reduce the required clock cycles of memory access. The MQ coder adopted the dynamic pipeline scheduling to reduce the latency of the pipeline stage. Thus the proposed architecture is suitable for the real-time applications.
　In the design of the ME, we first present a fast search algorithm, the grey prediction search (GrPS). With the aid of grey theory, the method can determine the motion vectors of image blocks more correctly and quickly. The experimental results show that the proposed algorithm performs better than other fast search algorithms in terms of picture quality, accuracy, computational complexity and coding efficiency. Then, we present a dedicated low-cost GrPS chip with 3-PE architecture to provide suitable solutions for MPEG-2 (720 pixels  480 lines, 30 frames/sec) in real time. Since GrPS performs better than other fast search algorithms, this low-cost GrPS chip is a good candidate for the real-time motion estimation.

CHAPTER　1　Introduction.....................................................1
1.1　Discrete wavelet Transform..............................................3
1.2　Embedded Block Coding with Optimized Truncation.........................5
1.3　Block Motion Estimation.................................................6
1.4　Organization of the Dissertation........................................7

CHAPTER　2　Hierarchical System Design Methodology...........................8
2.1　Introduction............................................................8
2.2　Hierarchical System Design Methodology.................................10
2.3　Hierarchical Specification Model.......................................12
2.4　Hierarchical Scheduling and Component Assignment.......................16
2.5　Virtual Component Model................................................24
2.6　Cycle-accurate Scheduling and Performance Annotation...................29
2.7　Super-state Transition Model...........................................31
2.8　Concluding Remarks.....................................................35

CHAPTER　3　Design of the Wavelet Video Coding System.......................36
3.1　Introduction...........................................................36
3.2　The Wavelet Video Coding System........................................38
　3.2.1　Wavelet Video Encoder..............................................38
　3.2.2　Wavelet Video Decoder..............................................43
3.3　Design of the Wavelet Video Coding System..............................45
　3.3.1　Hierarchical Specification Model of the Encoding System............45
　3.3.2　Approximated-time Scheduling for the Encoding System...............52
　3.3.3　Virtual Component Model of the Encoding System.....................55
3.4　Experiment Results.....................................................56
3.5　Concluding Remarks.....................................................57

CHAPTER　4　Orthogonal Wavelet Transform and Its Architectures..............58
4.1　Introduction...........................................................58
4.2　2-D Discrete Wavelet Transform.........................................60
　4.2.1　Forward Discrete Wavelet Transform.................................60
　4.2.2　Inverse Discrete Wavelet Transform.................................62
4.3　VLSI Architecture for 2-D DWT..........................................64
　4.3.1　The proposed pipelined architecture for 2-D DWT....................64
　4.3.2　Performance and Comparison.........................................71
4.4　VLSI Architecture for 2-D IDWT.........................................72
　4.4.1　Tree-Block Processing for IDWT.....................................73
　4.4.2　The proposed Architecture for 2-D IDWT.............................76
　　4.4.2.1　Column Filter..................................................77
　　4.4.2.2　Row Filter.....................................................82
　4.4.3　Scalable Architecture for the IDWT.................................85
　4.4.4　Results............................................................89
4.5　Concluding Remarks.....................................................90

CHAPTER　5　Design and Implementation of Biorthogonal DWT Module............91
5.1　Introduction...........................................................91
5.2　Lifting Scheme Discrete Wavelet Transform..............................93
5.3　Design of the DWT and IDWT Module......................................97
　5.3.1　The hierarchical specification model...............................98
　5.3.2　The virtual component model.......................................102
5.4　Filter architecture implemented by the filterbank structure...........108
　5.4.1　Forward 5/3 Filter Architecture by the Filterbank.................109
　5.4.2　Inverse 5/3 Filter Architecture by the Filterbank.................111
5.5　Filter architecture implemented by the lifting scheme.................112
　5.4.1　Forward 5/3 filter Architecture by the lifting scheme.............113
　5.4.2　Inverse 5/3 filter Architecture by the lifting scheme.............116
5.6　Scalability for 9/7 Biorthogonal Wavelet Transform....................118
　5.6.1　Filter Bank Structure.............................................119
　5.6.2　Lifting Scheme Structure..........................................121
5.7　Implementation and Results............................................124
5.8　Concluding Remarks....................................................127

CHAPTER　6　Design and Implementation of the EBCOT Module..................129
6.1　Introduction..........................................................129
6.2　EBCOT-T1 Algorithm....................................................132
　6.2.1　Context Information Generator.....................................133
　6.2.2　MQ Arithmetic Coding..............................................140
6.3　Design of the EBCOT Module............................................146
　6.3.1　The hierarchical specification model..............................146
　6.3.2　The virtual component model.......................................148
6.4　Architecture for Context Information Generator........................151
　6.4.1　Data organization and memory arrangement..........................154
　6.4.2　The architecture of three passes..................................157
6.5　Architecture for MQ Arithmetic Coder..................................161
　6.5.1　The Data flow and non-pipeline scheduling of MQ coder.............162
　6.5.2　The Datapath of the MQ Encoder....................................164
　6.5.3　The Non-pipeline Controller for MQ Coder..........................167
　6.5.4　The Dynamic pipeline Controller for MQ coder......................169
6.6　Hardware Implementation and Results...................................172
6.7　Concluding Remarks....................................................175

CHAPTER　7　Design and Implementation of the ME Module.....................176
7.1　Introduction..........................................................176
7.2　Block-Matching Algorithm..............................................178
7.3　The Grey Prediction Search Method.....................................181
　7.3.1　Finding the Predicted Motion Vector...............................182
　7.3.2　Determining the Final Motion Vector...............................185
7.4　Design of the ME Module...............................................189
　7.4.1　The hierarchical specification model..............................189
　7.4.2　The virtual component model.......................................190
7.5　Hardware Implementation for GrPS......................................193
　7.5.1　Memory Banks......................................................198
　7.5.2　Address Generators................................................199
　7.5.3　Motion Vector Generator...........................................201
　7.5.4　Controller........................................................207
　7.5.5　VLSI Implementation...............................................207
7.6　Concluding Remarks....................................................213

CHAPTER　8　CONCLUSIONS AND FUTURE WORK....................................214
8.1　Conclusions...........................................................214
8.2　Future Work...........................................................216

REFERENCES.................................................................218
　
                                    

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校內：2005-10-11公開
校外：2005-10-11公開

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