在本論文中，我們發展了一個全差動運算放大器的自動化合成軟體，這個合成軟體可以支援三種放大器的架構，包括了兩級式放大器(two-stage)、摺疊式疊接放大器(folded-cascode)以及兩級式疊接放大器(two-stage cascode)。此軟體以偏壓點的觀點來將查表法應用在元件的尺寸調整，因此它需要搭配電路模擬軟體來即時產生速查表。而為了有更好的效能，我們在軟體中融入了電路設計的經驗。在使用兩個1.2GHz UltraSPARC-III+處理器與2GB記憶體的作業平台中，我們的軟體通常可在3分鐘之內完成元件的尺寸調整。此外，我們更發展了一個輔助程序，來讓我們的合成軟體可以輕易地應用在更多的放大器架構。

In this thesis, an automated synthesis tool for fully differential OPAMPs is developed. The developed synthesis tool supports three OPAMP topologies: two-stage, folded-cascode, and two-stage cascode. The tool utilizes look-up tables for devices sizing from the viewpoint of biasing points. It needs to cooperate with the circuit simulator which can generate the look-up tables in real-time. For better performance, some circuit-design experience is merged in the tool. The executing time of devices sizing is within 3 minutes in general cases using two 1.2GHz UltraSPARC-III+ processors and 2GB memory. An auxiliary procedure is further developed to make the synthesis tool easily applied to more OPAMP topologies.

[1]　B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill,
　　　New York, USA, 2001.
[2]　E. Hjalmarson, “Studies on design automation of analog circuits -
　　　the design flow,” Ph.D. Dissertation, Linkopings University,
　　　Linkoping, Sweden, Dec. 2003.
[3]　M. G. R. Degrauwe, O. Nys, E. Dijkstra, et al., “IDAC: an interactive
　　　design tool for analog CMOS circuits,” IEEE J. Solid-State Circuits,
　　　vol. SC-22, no. 6, pp. 1106-1116, Dec. 1987.
[4]　R. Harjani, R. A. Rutenbar, and L. R. Carley, “Analog circuit
　　　synthesis and exploration in OASYS,” in Proc. IEEE Int. Conf.
　　　Computer Design, pp. 44-47, Oct. 1988.
[5]　R. Harjani, R. A. Rutenbar, and L. R. Carley, “OASYS: a framework
　　　for analog circuit synthesis,” IEEE Trans. Computer-Aided Design,
　　　vol. 8, no. 12, pp. 1247-1266, Dec. 1989.
[6]　F. El-Turky and E. E. Perry, “BLADES: an artificial intelligence
　　　approach to analog circuit design,” IEEE Trans. Computer-Aided
　　　Design, vol. 8, no. 6, pp. 680-692, June 1989.
[7]　C. A. Makris and C. Toumazou, “Analog IC design automation: part II -
　　　automated circuit correction by qualitative reasoning,” IEEE Trans.
　　　Computer-Aided Design, vol. 14, no. 2, pp. 239-254, Feb. 1995.
[8]　W. Nye, D. C. Riley, A. Sangiovanni-Vincentelli, and A. L. Tits,
　　　“DELIGHT.SPICE: an optimization-based system for the design of
　　　integrated circuits,” IEEE Trans. Computer-Aided Design, vol. 7,
　　　no. 4, pp. 501-519, April 1988.
[9]　F. Medeiro, F. V. Fernandez, R. Dominguez-Castro, and A. Rodriguez-
　　　Vazquez, “A statistical optimization-based approach for automated
　　　sizing of analog cells,” in IEEE/ACM Int. Conf. Computer-Aided
　　　Design, pp. 594-597, Nov. 1994.
[10]　M. Krasnicki, R. Phelps, R. A. Rutenbar, and L. R. Carley,
　　　“MAELSTROM: efficient simulation-based synthesis for custom analog
　　　cells,” in Proc. ACM/IEEE Design Automation Conf., pp. 945-950,
　　　June 1999.
[11]　R. Phelps, M. Krasnicki, R. A. Rutenbar, L. R. Carley, and J. R.
　　　Hellums, “Anaconda: simulation-based synthesis of analog circuits
　　　via stochastic pattern search,” IEEE Trans. Computer-Aided Design,
　　　vol. 19, no. 6, pp. 703-717, June 2000.
[12]　H. Y. Koh, C. H. Sequin, and P. R. Gray, “OPASYN: a compiler for
　　　CMOS operational amplifiers,” IEEE Trans. Computer-Aided Design,
　　　vol. 9, no. 2, pp. 113-125, Feb. 1990.
[13]　P. C. Maulik and L. R. Carley, “Automating analog circuit design
　　　using constrained optimization techniques,” in IEEE Int. Conf.
　　　Computer-Aided Design, pp. 390-393, Nov. 1991.
[14]　P. C. Maulik, L. R. Carley, and R. A. Rutenbar, “A mixed-integer
　　　nonlinear programming approach to analog circuit synthesis,”
　　　in Proc. ACM/IEEE Design Automation Conf., pp. 698-703, June 1992.
[15]　J. P. Harvey, M. I. Elmasry, and B. Leung, “STAIC: an interactive
　　　framework for synthesizing CMOS and BiCMOS analog circuits,” IEEE
　　　Trans. Computer-Aided Design, vol. 11, no. 11, pp. 1402-1417, Nov. 1992.
[16]　F. Medeiro, B. Perez-Verdu, A. Rodriguez-Vazquez, and J. L. Huertas,
　　　“A vertically integrated tool for automated design of ΣΔ modulators,”
　　　IEEE J. Solid-State Circuits, vol. 30, no. 7, pp. 762-772, July 1995.
[17]　E. S. Ochotta, R. A. Rutenbar, and L. R. Carley, “Synthesis of
　　　high-performance analog circuits in ASTRX/OBLX,” IEEE Trans.
　　　Computer-Aided Design, vol. 15, no. 3, pp. 273-294, Mar. 1996.
[18]　M. del M. Hershenson, S. P. Boyd, and T. H. Lee, “GPCAD: a tool
　　　for CMOS op-amp synthesis,” in IEEE/ACM Int. Conf. Computer-Aided
　　　Design, pp. 296-303, Nov. 1998.
[19]　M. del M. Hershenson, S. P. Boyd, and T. H. Lee, “Optimal design
　　　of a CMOS op-amp via geometric programming,” IEEE Trans. Computer-
　　　Aided Design, vol. 20, no. 1, pp. 1-21, Jan. 2001.
[20]　G. V. der Plas, G. Debyser, F. Leyn, et al., “AMGIE - a synthesis
　　　environment for CMOS analog integrated circuits,” IEEE Trans.
　　　Computer-Aided Design, vol. 20, no. 9, pp. 1037-1058, Sept. 2001.
[21]　G. Alpaydin, S. Balkir, and G. Dundar, “An evolutionary approach
　　　to automatic synthesis of high-performance analog integrated
　　　circuits,” IEEE Trans. Evolutionary Computation, vol. 7, no. 3,
　　　pp. 240-252, June 2003.
[22]　F. Silveira, D. Flandre, and P. G. A. Jespers, “A gm/ID based
　　　methodology for the design of CMOS analog circuits and its
　　　application to the synthesis of a silicon-on-insulator micropower
　　　OTA,” IEEE J. Solid-State Circuits, vol. 31, no. 9, pp. 1314-1319,
　　　Sep. 1996.
[23]　R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for
　　　Signal Processing, John Wiley & Sons, New York, USA, 1986.
[24]　B. Y. Kamath, R. G. Meyer, and P. R. Gray, “Relationship between
　　　frequency response and settling time of operational amplifiers,”
　　　IEEE J. Solid-State Circuits, vol. SC-9, no. 6, pp. 347-352, Dec. 1974.
[25]　S. Nicolson and K. Phang, “Improvement in biasing and compensation
　　　of CMOS OPAMPS,” ISCAS, 2004.
[26]　W. C. Black Jr., D. J. Allstot, and R. A. Reed, “A high performance
　　　low power CMOS channel filter,” IEEE J. Solid-State Circuits, vol.
　　　SC-15, no. 6, pp. 929-938, Dec. 1980.