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The Transform domain Weighted Interleave Vector Quantization (TwinVQ) is a VQ based coding tool designed to provide good quality at an extremely low bitrate (at or below 16kbps). However, the heavy computational complexity of this encoder is its main drawback. In this thesis, VLSI architectures are proposed to speed up the two-channel conjugate structure weighted vector quantization computation. This dedicated hardware is designed to conquer the high computational load due to vector quantization and is based on an improved distributed arithmetic architecture. The error distance computation in weighted conjugate vector quantization can be converted to inner product form and can be efficiently carried out with distributed arithmetic architecture. Compared with direct computation of weighted conjugate structure vector quantization, our proposed architecture is almost free of multiplier and is more practical to be implemented with FPGA. With our proposed VLSI architecture, over 2000 subframes can be weighted vector quantized within one second while the circuit is working at 20MHz.

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