成功大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	陳瑞嶸 Chen, Rei-Lung
論文名稱：	單晶片系統測試平台之可重組廣播式掃描架構 A Reconfigurable Broadcast Scan Architecture for SOC Test Platforms
指導教授：	李昆忠 Lee, Kuen-Jong
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	72
中文關鍵詞：	測試、掃瞄鏈、輸入腳位壓縮技術、單晶片系統測試平台
外文關鍵詞：	SOC test platform, input reduction technique, scan chain, testing
相關次數：	點閱：70 下載：1
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

　　隨著系統單晶片功能的複雜化，晶片中的矽智產核心電路數目逐漸增加，然而，系統單晶片與測試儀器之間的資料頻寬卻是有限的，導致過長的測試時間成為測試一個系統單晶片的瓶頸所在。
　　
　　在本篇論文中，我們提出一個嶄新的輸入腳位壓縮技術，名為可重組廣播式掃瞄技術。此技術為一適用於系統單晶片的方法，不需更動原本核心電路中的設計，因此核心電路中的掃瞄鏈數目可由設計者任意決定。主要概念為在外部輸入埠和內部掃瞄鏈間增設一可重組式邏輯電路，用以在不同的測試區段間，將測試資料廣播至不同的掃瞄鏈中。同時輸出腳位壓縮技術也被整合，為系統單晶片提供一個完整的掃瞄架構。如實驗結果所示，當此技術被應用在內建200條掃瞄鏈的最大5個ISCAS’89標準電路時，輸入埠的平均數目將少於7，顯示此技術在解決系統單晶片平台上測試存取機制頻寬不足的問題有很大的助益，且將有效減少測試時間和測試資料量。

　The number of intellectual property (IP) cores in a chip increases with the function complicating in SOC designs. The bottleneck of testing a system-on-a-chip (SOC) is the long test time arisen from the limited test data bandwidth between the tester and the SOC.
　　
　A novel scan-based design technique called the “Reconfigurable Broadcast Scan Technique” is proposed in this thesis. This scan technique can be applied to the cores in an SOC without modifying the cores, and hence the number of scan chains of each core can be arbitrarily determined by the designer. Our basic idea is to add a reconfiguration logic between the external scan-in ports and the internal scan chains of the cores such that the test data can be broadcast to different scan chains during different test sessions. The integration with the output reduction technique provides the complete scan architecture for the SOC test platforms. With this method the insufficient TAM width problem for an SOC which may exist in the recently developed test platforms or the on-chip ATE can be effectively solved. Experimental results show that the number of scan-in ports can be reduced to no more than 7 on the 5 largest ISCAS’89 benchmark circuits with 200 scan chains. We also show that with our reconfiguration technique the test time and test volume can be significantly reduced.

Table of Contents
Chapter 1 Introduction...................................................1
　1.1. Motivation........................................................1
　1.2. Introduction to Reconfigurable Broadcast Scan Technique...........2
　1.3. Organization of Thesis............................................3
Chapter 2 Background and Previous Work...................................5
　2.1. Background........................................................5
　　2.1.1. Embedded-Processor-Driven Platform for SOC Testing............5
　　2.1.2. Broadcast scan................................................8
　2.2. Previous work....................................................10
Chapter 3 Introduction to Reconfigurable Broadcast Scan Architecture....15
　3.1. Overview of the Reconfigurable Broadcast Scan Architecture.......15
　3.2. R-broadcast scan Technique (Phase I).............................18
　　3.2.1. Build the Chain Constraints Table............................19
　　3.2.2. Construct the Weighted Conflict Graph........................23
　　3.2.3. Procedure of Assigning Scan Chains to Scan-in Ports..........24
　　3.2.4. Another Chain Configuration..................................30
　　3.2.5. Construct the R-broadcast Scan Architecture (Phase I)........31
　3.3. R-broadcast scan Technique (Phase II)............................34
　　3.3.1. Building the New Chain Constraints Table.....................35
　　3.3.2. The XOR Map and the Map of X-Chains..........................37
　　3.3.3. Procedure of Inserting XOR gates.............................38
　　3.3.4. Construct the R-broadcast Scan Architecture (Phase II).......41
Chapter 4 Integration of Input & Output Reduction Techniques............43
　4.1. Input Reduction Technique........................................43
　4.2. Output Reduction Technique.......................................45
　4.3. The Whole Scan Architecture......................................46
Chapter 5 Experimental Results..........................................48
　5.1. The Experimental Results of the Phase I..........................48
　5.2. The Experimental Results of the Phase II.........................56
　5.3. The Experimental Results of the Whole Architecture...............59
　5.4. Comparison with Other Works......................................62
　5.5. The Experimental Results on nnARM................................66
Chapter 6 Conclusions...................................................68
References..............................................................69


                                    

[1]Y.-T. Hung and K.-J. Lee, “An Embedded-Processor-Driven Platform for SOC Testing,” Proc. VLSI Design/CAD Symp., 2002.
[2]K.-J. Lee, C.-Y. Chu and Y.-T. Hung, “An Embedded Processor Based SOC Test Platform” Proc. ISCAS, 2005.
[3]A. Jas, J. Ghosh-Dastidar and N.A. Touba, “Scan vector compression/decompression using statistical coding,” Proc. VLSI Test Symp., pp.114-120, 1999.
[4]A. Jas and N. A. Touba, “Test vector decompression via cyclical scan chains and its application to testing core-based design,” Proc. Int. Test Conf., pp.458-464, 1998.
[5]A. Chandra and K. Chakrabarty, “System-on-a-chip test data compression and decompression architectures based on Golomb codes,” IEEE Trans. on Computer-Aided Design, vol. 20, pp.355-368, 2001.
[6]A. Chandra and K. Chakrabarty, “Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression,” Proc. VLSI Test Symp., pp.42-47, 2001.
[7]A. Jas, J. Ghosh-Dastidar, M.-E. Ng, and N.A. Touba, “An Efficient Test Vector Compression Scheme Using Selective Huffman Coding,” IEEE Trans. on Computer-Aided Design, vol. 22, pp.797-806, 2003.
[8]B. Koenemann, “LFSR-Coded Test Patterns for Scan Designs,” Proc. European Test Conf., pp.237-242, 1991.
[9]C. V. Krishna, A. Jas, and N. A. Touba, “Test Vector Encoding Using Partial LFSR Reseeding,” Proc. Int’l. Test Conf., pp.885-893, 2001.
[10]G. Mrugalski, J. Rajski, J. Tyszer, “High Speed Ring Generators and Compactors of Test Data,” Proc. VLSI Test Symp., pp. 57-62, 2003.
[11]K. J. Lee, J. J. Chen and C. H. Huang, “Using a single input to support multiple scan chains,” Proc. ICCAD Conf., pp. 74-78, 1998.
[12]K. J. Lee, J. J. Chen and C. H. Huang, “Broadcasting Test Patterns to Multiple Circuits,” IEEE Trans. on Computer-Aided Design, pp. 1793-1802, 1999.
[13]I. Hamzaoglu and J. H. Patel, “Reducing Test Application Time for Full Scan Embedded Cores,” Proc. Int’l Symp. on Fault-Tolerant Computing, pp. 260-267, 1999.
[14]A. R. Pandey and J.H. Patel, “Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Design,” Proc. VLSI Test Symp., pp.9-15., 2002.
[15]M.A. Shah and J.H Patel, “Enhancement of the Illinois scan architecture for use with multiple scan inputs” Proc. VLSI Test Symp., pp.167-172, 2004.
[16]I. Bayraktaroglu and A. Orailoglu, “Test Volume and Application Time Reduction through Scan Chain Concealment,” Proc. Design Automation Conf., pp.151-155, 2001.
[17]I. Bayraktaroglu and A. Orailoglu, “Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression”, Proc. VLSI Test Symp., pp.113-118, 2003.
[18]W. Rao, A. Orailoglu and G. Su, “Frugal linear network-based test decompression for drastic test cost reductions” Proc. ICCAD Conf., pp.721-725, 2004.
[19]Li Lei, K. Chakrabarty, S. Kajihara and S. Swaminathan, “Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores” VLSI Design Conf., pp. 53-58, 2005.
[20]K. Miyase and S. Kajihara, “Optimal Scan Tree Construction with Test Vector Modification for Test Compression”, Proc. Asian Test Symp., pp. 136-141, 2003.
[21]K. Miyase, S. Kajihara, and S. M. Reddy, “Multiple Scan Tree Design with Test Vector Modification,” Proc. Asian Test Symp., pp. 76-81, 2004.
[22]C. Y. Chen and K. J. Lee, “Output Compaction Techniques for Multiple Scan Chain Designs”, NCKU master thesis, 2005.
[23]SynTest Technology, Inc., TurboScan User Guide, http://www.syntest.com/.
[24]Open Cores Website, http://www.opencores.org/projects.cgi/web/nnARM/overview.

校內：2008-08-26公開
校外：2015-08-26公開

簡易檢索 / 詳目顯示

相關論文