直流無刷馬達由於其高功率密度、壽命長及高效率等特性，在節能減碳的潮流下，逐漸取代有刷馬達而被廣泛使用。本論文針對直流無刷馬達控制與驅動端設計了一顆專用晶片，包含驅動控制中所需之控制迴路方塊、換相邏輯與其他周邊模組，並透過現場可程式邏輯陣列(FPGA)驗證此IP功能。本論文使用之驗證方法有二，一為使用MATLAB/Simulink與FPGA做軟硬體混合模擬驗證，二為實際燒錄至FPGA中，並搭配功率後級變頻器電路與無刷直流馬達進行實作驗證。於驗證結果無誤後，進行晶片設計中的後段工程，實際製作成專用積體電路(ASIC) 。若能大量使用，與傳統使用微控制器之解決方案相比，ASIC可減少馬達驅動成本與開發複雜度。
本論文結合了馬達驅動、伺服控制及IC設計技術，自系統層次理論分析到晶片電路實作，完成晶片佈局與馬達控制驅動之各項相關硬體電路設計。實作與模擬結果皆顯示本論文所設計之IC具有良好性能，可實際應用於直流無刷馬達驅動器實作。

Due to its attractive features such as high power density, long duration and high efficiency, the Brushless DC Motor (BLDCM) has gradually replaced the conventional brush DC motor and has been widely used in home appliances, office equipment, industrial applications and vehicles, and more. This thesis designs an Application Specific Integrated Circuit (ASIC) that can be used in motor control and drive application. The ASIC designed in this thesis includes all the necessary circuit blocks such as switching algorithm, controllers, and peripheral modules. In addition, all the functionalities are verified by using the Field Programmable Gate Array (FPGA). Moreover, two methods are used in this thesis to verify the designed IP. One is to perform MATLAB/Simulink and FPGA Co-Simulation, the other is to download the IP into an FPGA and conduct the experimental verification on a BLDCM and its inverter circuit. After the verifications are completed, one can focus on the back-end engineering in IC design flow, and then proceed to make a real chip. If the demand of ASICs reaches a certain level, compared with traditional microcontroller based solutions, the ASIC based solution can reduce the cost and complexity when implementing a BLDC motor drive.
In summary, this thesis focuses on combining the techniques related to BLDC motor drive, servo control and IC design. In particular, all necessary works for the implementation of a BLDC motor drive ASIC such as system-level simulation, theoretical analysis, circuit design, and chip layout have been completed. Both simulation and experimental results show that the ASIC developed in this thesis exhibits satisfactory performance. It suggests the ASIC developed in this thesis is a suitable solution for utilizing the BLDC motor drive.

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