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研究生: 張晉維
Chang, Chin-Wei
論文名稱: 適用於非揮發性微處理器系統之節能效益及性能探勘虛擬平台
A Nonvolatile Processor Virtual Platform for Energy Efficiency and Performance Exploration
指導教授: 邱瀝毅
Chiou, Lih-Yih
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2019
畢業學年度: 107
語文別: 中文
論文頁數: 45
中文關鍵詞: 非揮發性微處理器非揮發性靜態隨機存取記憶體電子系統層級功耗模型物聯網架構探勘
外文關鍵詞: non-volatile microprocessor, non-volatile SRAM, electronic system level, power model, internet of things, architecture exploration
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  • 隨著物聯網的發展,大量小型化的感知節點散佈在人們的生活周遭、罕無人跡之處。小型化的裝置電池容量有限,此外,記憶體的功耗問題日益嚴重,非揮發性微處理器系統能夠減輕這項問題,但非揮發性記憶體元件本身使用壽命與揮發性記憶體元件相比仍有待改善,需要先藉由架構及控制方法克服這項問題。適用於非揮發性微處理器系統之虛擬平台能夠在系統正成晶片之前對架構、控制演算法進行探勘。
    本論文提出之虛擬平台,針對非揮發性微處理器系統建立週期近似行為模型,並加入功耗及時序模型,形成一個能夠對節能效益及性能進行探勘的虛擬平台。電子系統層級的功耗分析可以幫助系統層級設計者,在早期設計階段針對系統進行功率優化與開發控制演算法,不必等到成品完成。此平台包含RISC-V指令集之微處理器及非揮發性靜態隨機存取記憶體,並具有模擬彈性和可調性,使用者可以調整平台參數,執行不同特性的基準測試程式,對非揮發性微處理器架構、功耗進行分析。

    關鍵字 : 非揮發性微處理器、非揮發性靜態隨機存取記憶體、電子系統層級、功耗模型、物聯網、架構探勘

    SUMMARY

    With the development of the Internet of Things, a large number of miniaturized sensor nodes are scattered around people's lives and uninhabited places. These miniaturized devices only have limited battery capacity. Furthermore, the power consumption of memory is getting worse than ever before. Nonvolatile processor systems can mitigate this problem. However, the endurance cycle of non-volatile memory components still needs to be further enhanced. Before that, this problem needs to be overcame by architecture and control methods. The nonvolatile-processor virtual platform can be used to explore architecture and energy-optimization algorithms before the system is actually fabricated in silicon.
    In this work, we proposed a virtual platform, consisting of a cycle-approximate behavior model, with power and timing model for evaluating nonvolatile processor systems. This platform can be used to explore energy efficiency and performance. Power consumption analysis at the electronic system level can help system-level designers optimize power consumption and develop control algorithms for the system in early phase of design. The platform includes the microprocessor of the RISC-V instruction set and non-volatile SRAM with flexibility and configurability, allow developers adjust the platform parameters, execute benchmark programs with different characteristics, and analyze non-volatile microprocessor architecture and power consumption.

    Keywords : non-volatile microprocessor, non-volatile SRAM, electronic system level, power model, internet of things, architecture exploration

    摘要 i 誌謝 vi 目錄 vii 表目錄 ix 圖目錄 x 第1章 緒論 1 1.1 研究概觀 1 1.2 研究動機 3 1.3 研究貢獻 5 1.4 論文架構 5 第2章 相關研究背景 6 2.1 非揮發性記憶體及微處理器 6 2.1.1 低功耗微處理器 6 2.1.2 非揮發性記憶體 8 2.1.3 非揮發性微處理器 10 2.2 即時作業系統 11 2.2.1 即時作業系統 11 2.2.2 FreeRTOS 12 2.2.3 任務調度 12 2.2.4 任務切換及記憶體分配 13 2.3 RISC-V指令集之微處理器 14 2.4 電子系統層級虛擬平台及功率模型 15 2.4.1 電子系統層級平台 15 2.4.2 功率模型層級 16 第3章 相關文獻探討 18 3.1 在ESL環境下的虛擬平台 18 3.1.1 基於模型的SoC設計 18 3.1.2 具擴展性和可調性的虛擬原型 19 3.2 加入功耗模型之ESL平台 21 3.3 相關文獻總結 22 第4章 非揮發性微處理器系統之模型建立 23 4.1 問題描述 23 4.2 目標虛擬平台架構 23 4.3 非揮發性微處理器模型 24 4.3.1 RISC-V指令集之微處理器核心 25 4.3.2 非揮發性靜態隨機存取記憶體 26 4.3.3 其他模組 28 4.4 動態記憶體區塊管理[3] 29 第5章 實驗結果與分析 31 5.1 實驗環境設定 31 5.1.1 平台硬體配置 31 5.1.2 軟體環境 31 5.2 實驗一 物聯網系統應用情境實驗 32 5.2.1 參數設定 32 5.2.2 應用程式情境[3] 32 5.2.3 記憶體區塊動態開啟數量觀察 34 5.2.4 記憶體區塊開關次數及週期觀察 35 5.2.5 記憶體功耗分析 36 5.2.6 額外代價分析 37 第6章 結論與未來研究 39 6.1 結論 39 6.2 未來工作 39 參考文獻 41

    [1] J.Gubbi, R.Buyya, S.Marusic, and M.Palaniswami, “Internet of Things (IoT): A vision, architectural elements, and future directions,” Futur. Gener. Comput. Syst., vol. 29, no. 7, pp. 1645–1660, Sep.2013.
    [2] M. H.Asghar, N.Mohammadzadeh, A.Negi, and T.Kazerouni, “Principal ingredients and framework of Internet of Things (IoT),” in Proc. Twelfth International Conference on Wireless and Optical Communications Networks (WOCN), 2015, pp. 1–6.
    [3] Y.-P.Chang, “Dynamic Memory Block Management for Energy-Efficient Nonvolatile Processor with Real-Time Operating Systems,” M.S. thesis, EE, National Cheng Kung University, Tainan, Taiwan, 2018.
    [4] “MSP430FR596x , MSP430FR594x Mixed-Signal Microcontrollers,” 2018. [Online]. Available: http://www.ti.com/lit/ds/symlink/msp430fr5969.pdf
    [5] “STM32L496xx,” 2018. [Online]. Available: https://www.st.com/content/ccc/resource/technical/document/datasheet/group3/3f/73/19/d1/d4/9e/48/34/DM00284211/files/DM00284211.pdf/jcr:content/translations/en.DM00284211.pdf
    [6] “Datasheet S7G2 Microcontroller Group Datasheet Renesas Synergy TM Platform Synergy Microcontrollers,” 2018. [Online]. Available: https://www.renesas.com/tw/zh/doc/products/renesas-synergy/doc/r01ds0262eu0140-synergy-s7g2.pdf
    [7] C. R.Huang, K. L.Wu, C. H.Wu, and L. Y.Chiou, “Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme,” in Proc. - IEEE Int. Symp. Circuits Syst., vol. 2018-May, pp. 1–4, 2018.
    [8] E.Morifuji, T.Yoshida, M.Kanda, S.Matsuda, S.Yamada, and F.Matsuoka, “Supply and threshold-voltage trends for scaled logic and SRAM MOSFETs,” IEEE Trans. Electron Devices, vol. 53, no. 6, pp. 1427–1432, 2006.
    [9] T.-K.Chien, L.-Y.Chiou, S.-S.Sheu, J.-C.Lin, C.-C.Lee, T.-K.Ku, M.-J.Tsai, and C.-I.Wu, “Low-Power MCU With Embedded ReRAM Buffers as Sensor Hub for IoT Applications,” IEEE J. Emerg. Sel. Top. Circuits Syst., vol. 6, no. 2, pp. 247–257, Jun.2016.
    [10] P.-F.Chiu, M.-F.Chang, C.-W.Wu, C.-H.Chuang, S.-S.Sheu, Y.-S.Chen, and M.-J.Tsai, “Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications,” IEEE J. Solid-State Circuits, vol. 47, no. 6, pp. 1483–1496, Jun.2012.
    [11] Y.Shuto, S.Yamamoto, and S.Sugahara, “New power-gating architectures using nonvolatile retention: Comparative study of nonvolatile power-gating (NVPG) and normally-off architectures for SRAM,” In Proc. IEEE Int. Conf. Microelectron. Test Struct., vol. 2016-May, pp. 136–141, 2016.
    [12] “GitHub - syntacore/scr1: SCR1 is a high-quality open-source RISC-V MCU core in Verilog.” . [Online]. Available: https://github.com/syntacore/scr1
    [13] “GitHub - riscv-boom/riscv-boom: BOOM: Berkeley Out-of-Order Machine.” . [Online]. Available: https://github.com/riscv-boom/riscv-boom
    [14] “GitHub - chipsalliance/rocket-chip: Rocket Chip Generator.” . [Online]. Available: https://github.com/chipsalliance/rocket-chip
    [15] “SystemC.” [Online]. Available: https://www.accellera.org/downloads/standards/systemc. [Accessed: 21-Aug-2019].
    [16] “TLM 2.0.” [Online]. Available: https://www.accellera.org/downloads/standards/systemc. [Accessed: 21-Aug-2019].
    [17] H.Blume, D.Becker, L.Rotenberg, M.Botteck, J.Brakensiek, and T. G.Noll, “Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures,” J. Syst. Archit., vol. 53, no. 10, pp. 689–702, 2007.
    [18] N.Kroupis and D.Soudris, “FILESPPA: Fast Instruction Level Embedded System Power and Performance Analyzer,” Microprocess. Microsyst., vol. 35, no. 3, pp. 329–342, 2011.
    [19] M.Sami, D.Sciuto, C.Silvano, and V.Zaccaria, “An instruction-level energy model for embedded VLIW architectures,” IEEE Trans. Comput. Des. Integr. Circuits Syst., vol. 21, no. 9, pp. 998–1010, 2002.
    [20] D.Araki, A.Nakamura, and M.Miyama, “Model-based SoC design using ESL environment,” In Proc. Int. SoC Des. Conf. ISOCC 2010, pp. 83–86, 2010.
    [21] V.Herdt, D.Große, H. M.Le, and R.Drechsler, “Extensible and Configurable RISC-V Based Virtual Prototype,” In Proc. Forum Specif. Des. Lang., vol. 2018-Septe, 2018.
    [22] S.Yoon, K.Park, W.Kim, and H.Cho, “Power estimation of cryptographic modules using virtual SoC platform,” In Proc. Int. Conf. Electron. Inf. Commun. ICEIC 2018, vol. 2018-Janua, pp. 1–3, 2018.
    [23] T.-K.Chien, L.-Y.Chiou, S.-S.Sheu, J.-C.Lin, C.-C.Lee, T.-K.Ku, M.-J.Tsai, and C.-I.Wu, “Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches,” in Proc. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2017, pp. 1–6.
    [24] T.-K.Chien, L.-Y.Chiou, S.-S.Sheu, J.-C.Lin, C.-C.Lee, T.-K.Ku, M.-J.Tsai, and C.-I.Wu, “Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F2/Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM,” IEEE Trans. Circuits Syst. II Express Briefs, vol. 65, no. 9, pp. 1234–1238, 2018.
    [25] S. N.Pakzad, S.Kim, G.Fenves, and S.Glaser, “Multi-purpose wireless accelerometers for civil infrastructure monitoring,” In Proc. of the 5th International Workshop on Structural Health Monitoring (IWSHM 2005), 2005. [Online]. Available: http://www.eecs.berkeley.edu/~binetude/work/IWSHM.pdf.
    [26] E.Sazonov, K.Janoyan, and R.Jha, “Wireless intelligent sensor network for autonomous structural health monitoring,” in Proc. Smart Structures and Materials: Smart Sensor Technology and Measurement Systems, 2004, vol. Proceeding, p. 305.
    [27] E.Sazonov, Haodong Li, D.Curry, and P.Pillay, “Self-Powered Sensors for Monitoring of Highway Bridges,” IEEE Sens. J., vol. 9, no. 11, pp. 1422–1429, Nov.2009.
    [28] K. S.Kumar, B.Yazdanpanah, and P. R.Kumar, “Removal of noise from electrocardiogram using digital FIR and IIR filters with various methods,” in Proc. International Conference on Communications and Signal Processing (ICCSP), 2015, pp. 0157–0162.
    [29] D.Bhowmik, P.Garcia, A.Wallace, R.Stewart, and G.Michaelson, “Power efficient dataflow design for a heterogeneous smart camera architecture,” in Proc Conference on Design and Architectures for Signal and Image Processing (DASIP), 2017, vol. 2017-Septe, pp. 1–6.
    [30] M.Lecca, Y.Zou, and M.Gottardi, “A low power smart camera for video surveillance and forensic applications,” in Proc. International Conference on Engineering, Technology and Innovation (ICE/ITMC), 2017, pp. 626–631.

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