| 研究生: |
張晉維 Chang, Chin-Wei |
|---|---|
| 論文名稱: |
適用於非揮發性微處理器系統之節能效益及性能探勘虛擬平台 A Nonvolatile Processor Virtual Platform for Energy Efficiency and Performance Exploration |
| 指導教授: |
邱瀝毅
Chiou, Lih-Yih |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2019 |
| 畢業學年度: | 107 |
| 語文別: | 中文 |
| 論文頁數: | 45 |
| 中文關鍵詞: | 非揮發性微處理器 、非揮發性靜態隨機存取記憶體 、電子系統層級 、功耗模型 、物聯網 、架構探勘 |
| 外文關鍵詞: | non-volatile microprocessor, non-volatile SRAM, electronic system level, power model, internet of things, architecture exploration |
| 相關次數: | 點閱:71 下載:0 |
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隨著物聯網的發展,大量小型化的感知節點散佈在人們的生活周遭、罕無人跡之處。小型化的裝置電池容量有限,此外,記憶體的功耗問題日益嚴重,非揮發性微處理器系統能夠減輕這項問題,但非揮發性記憶體元件本身使用壽命與揮發性記憶體元件相比仍有待改善,需要先藉由架構及控制方法克服這項問題。適用於非揮發性微處理器系統之虛擬平台能夠在系統正成晶片之前對架構、控制演算法進行探勘。
本論文提出之虛擬平台,針對非揮發性微處理器系統建立週期近似行為模型,並加入功耗及時序模型,形成一個能夠對節能效益及性能進行探勘的虛擬平台。電子系統層級的功耗分析可以幫助系統層級設計者,在早期設計階段針對系統進行功率優化與開發控制演算法,不必等到成品完成。此平台包含RISC-V指令集之微處理器及非揮發性靜態隨機存取記憶體,並具有模擬彈性和可調性,使用者可以調整平台參數,執行不同特性的基準測試程式,對非揮發性微處理器架構、功耗進行分析。
關鍵字 : 非揮發性微處理器、非揮發性靜態隨機存取記憶體、電子系統層級、功耗模型、物聯網、架構探勘
SUMMARY
With the development of the Internet of Things, a large number of miniaturized sensor nodes are scattered around people's lives and uninhabited places. These miniaturized devices only have limited battery capacity. Furthermore, the power consumption of memory is getting worse than ever before. Nonvolatile processor systems can mitigate this problem. However, the endurance cycle of non-volatile memory components still needs to be further enhanced. Before that, this problem needs to be overcame by architecture and control methods. The nonvolatile-processor virtual platform can be used to explore architecture and energy-optimization algorithms before the system is actually fabricated in silicon.
In this work, we proposed a virtual platform, consisting of a cycle-approximate behavior model, with power and timing model for evaluating nonvolatile processor systems. This platform can be used to explore energy efficiency and performance. Power consumption analysis at the electronic system level can help system-level designers optimize power consumption and develop control algorithms for the system in early phase of design. The platform includes the microprocessor of the RISC-V instruction set and non-volatile SRAM with flexibility and configurability, allow developers adjust the platform parameters, execute benchmark programs with different characteristics, and analyze non-volatile microprocessor architecture and power consumption.
Keywords : non-volatile microprocessor, non-volatile SRAM, electronic system level, power model, internet of things, architecture exploration
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校內:2024-08-31公開