本篇論文以軟體的方式，發展一套靜態的二元碼轉譯系統，其最大的特性是可以藉由替換來源端與目的端平台的指令集描述檔，很容易地實現相容於多個來源端與多個目的端平台的特性。
這個系統的架構可分為前端、中端和後端三個部份，前端我們是藉由UQBT系統的前級去實現，它可以將一個可執行的程式轉為中間語言HRTL(High-level Register Transfer Lists)；而本系統發展的中、後端與一般編譯器實作的方式相似，中端的部份由三個元件組成，字詞分析器會讀進前端輸出的中間語言HRTL，轉為一連串的基本單元編碼，送至語法分析器建構成一棵二元樹，再由二元樹優化器作最佳化；後端的部份由二個元件組成，樣本比對器能從中端輸出的二元樹裡，找出可以被合併的指令，再由程式碼產生器輸出目標平台的組合語言碼。目前我們輸出ARM平台的組合語言程式碼，送至ARM Developer Suite (ADS)這套應用程式上作驗證，並將其輸出的結果與來源端的執行檔及原始C程式碼在ADS上模擬的結果作比較。
在近年來很熱門的虛擬機器(Virtual Machines)研究中，二元碼轉譯亦是其中一個重要的技術，我們也希望藉由這樣一個具彈性、多來源與多目標的二元碼轉譯系統實作，能更進一步涉獵虛擬機器這個領域。

In this paper we've developed a binary translation system, using static approach. That has the ability of resourceable and retargetable features.
This system can be divided into 3 parts, Front-end, Middle-end and Back-end. The front-end of UQBT system is adopted in our system that translates executable file into an intermediate language, HRTL (High-level Register Transfer Lists). Middle-end is composed of three components, Lexical Analyzer, Syntax Analyzer and Tree Optimizer. Lexical analyzer loads HRTL as input and translates it in a form of token-encoding. Then these token-encoding were delivered to Syntax Analyzer to create a binary tree. This binary tree will be optimized by Tree Optimizer. Middle-end is composed of two components, Pattern Matcher and Code Generator. Pattern Matcher looks for combinable instructions in binary tree and generates target assembly code via the Code Generator. Here, we take ARM as our ISA. The translated assembly code compared with source C code can be verified on ARM Developer Suite (ADS).
In recent years, virtual machine researches are rapidly growing in popularity, binary translation is one of its important techniques. We hope to dabble in the field of virtual machine by the research of resourceable and retargetable binary translation system.

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