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研究生：	蘇弘毅 Su, Hong-Yi
論文名稱：	應用於多媒體之動態可重新架構化硬體平台設計 Run-Time Reconfigurable Hardware Platform Design for Multimedia Applications
指導教授：	周哲民 Jou, Jer-Min
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	91
中文關鍵詞：	動態、平台設計、多媒體、可重新架構
外文關鍵詞：	Reconfigurable, Platform, Run-Time, Multimedia
相關次數：	點閱：88 下載：2
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由於時間的限制與昂貴的光罩成本，IC設計工程師面臨的許多關於如何加快研發速度並盡其所的增加IP的可重複利用性(reusability)等等難題。而可重置架構(reconfigurable architectures)正好提供了這一切的解答。
在此篇論文之中，為了快速的多媒體應用之運算，我們提供了一個高效率的媒體之動態可重新架構化硬體平台，設計者可以非常容易的重覆使用我們的平台去驗證許多的多媒體設計。最後從實驗結果之中，我們將可以看到軟硬體共同執行的結果最快可以比純軟體執行快了8.29倍。

Due to the pressure of TTM and expensive mask cost, IC designers are forced to shorten design process time and try their best to increase the reusability of IPs. The reconfigurable architecture provides extremely advantages such as reducing the cost, time and complexity of design, and diminishing the difficulties for the integration on IP components. Here, for fast multimedia processing we presented a high performance on-line reconfigurable hardware platform. With it, the hardware designers can easily and efficiently design different multimedia applications into hardware, and then, easy reusing and modifications. We have verified the platform by mapping many multimedia applications into the platform, and experimental results show that the average speed up ratio is 8.29 compared with the software-only design approach.

Chapter 1. Introduction	                                                1
Chapter 2. The Property of Reconfigurable Architecture System	        4
     2.1 Statically and Dynamically Reconfigurable System	        5
       2.1.1 Statically Reconfigurable Systems	                        6
       2.1.2 Dynamically Reconfigurable Systems	                        7
     2.2 Granularity of the Reconfigurable System	                8
     2.3 Depth of Programmability	                                8
     2.4 Tightly-Coupled and Loosely-Coupled Reconfigurable System	9
     2.5 Self-Reconfigurable System	                                9
Chapter 3. Run-Time Reconfigurable Hardware Platform	                10
     3.1 Functional Controller	                                        11
     3.2 Function Memory	                                        13
     3.3 Context Memory	                                                14
     3.4 Input Data Buffer	                                        15
     3.5 Result Buffer	                                                16
     3.6 Reconfigurable Interconnecting Network	                        17
     3.7 Functional Units	                                        21
       3.7.1 Floating Adder	                                        23
       3.7.2 Floating Multiplication	                                25
       3.7.3 Floating Division	                                        26
     3.8 HW-SW Co-Execution	                                        29
Chapter 4. The Communication of HW and SW	                        31
     4.1 Interrupted HW/SW Co-communication	                        33
       4.1.1 Interrupt Controller	                                34
       4.1.2 Interrupt Handler and Interrupt Service Routine	        36
     4.2 Burst-Style Data Transfer	                                41
       4.2.1 The LDM、STM Register List	                               41
       4.2.2 Addressing Modes	                                        42
       4.2.3 LDM、STM Assembler Syntax	                               43
       4.2.4 Burst Type Data Transfer Example	                        44
Chapter 5. ARM Integrator and AHB BUS Architecture	                47
     5.1 ARM Integrator	                                                47
     5.2 ARM Integrator AP	                                        51
     5.3 ARM Integrator LM (Logic Module)	                        53
     5.4 ARM Integrator CM (Core Module) 920T	                        56
     5.5 AMBA AHB Bus Architecture	                                59
Chapter 6. Mapping and Experiment Results	                        62
     6.1 Applications 1: MP3 Encoder	                                62
       6.1.1 Introduction to MP3 Encoding	                        63
       6.1.2 WAVE PCM Sound-File Format	                                65
       6.1.3 MP3 Encoder Analysis	                                67
     6.2 Applications 2: MP3 Decoder	                                72
       6.2.1 Introduction to MP3 Decoding	                        72
       6.2.2 MP3 Decoder Analysis	                                75
     6.3 Applications 3: 8-Point FFT	                                77
     6.4 Applications 4: RCM-DWT and RCM-IDWT	                        79
     6.5 Mapping and Experiment Results	                                81
       6.5.1 The Method of Mapping an Example to Reconfigurable HW	81
       6.5.2 The Experiment Result and Analysis	                        85
Chapter 7. Conclusion	                                                90
Reference	                                                        91


                                    

[1] AMBA specification rev2.0. ARM Limited.
[2] Guangming Lu. “Modeling, Implementation and Scalability of the MorphoSys Dynamically Reconfigurable Computing Architecture”, http://portal.acm.org/portal.cfm , 2000.
[3] ARM INTEGRATOR /AP user guide. ARM Limited.
[4] Jer-Min Jou. "Reconfigurable SoC Architectures," Proceedings of the 2003 VLSI Design/CAD Symposium, 2003.
[5] ARM INTEGRATOR/CM920T-ETM INTEGRATOR/CM940T-ETM user guide ARM Limited.
[6] ARM INTEGRATOR/LM-XCV600E+ INTEGRATOR/LM-EP20K600E+ user guide ARM Limited.
[7] ARM MULTI-ICE version 2.2 user guide ARM Limited.
[8] ARM developer suite version 1.1 compiler, linker, and utilities guide ARM Limited.
[9] David A. Patterson and John L. Hennessy, “computer organization & design the hardware/software interface”.
[10] Pramod Chandraiah, Hans Gunar Schirner, Nirupama Srinivas and Rainer Doemer. “System-On Chip Modeling and Design -- A case study on MP3 Decoder”, 2004
[11] M. Aksit. “Dynamic, Adaptive and Reconfigurable Systems Overview and Prospective Vision”, 2003 IEEE
[12] Behrooz Parhami.“computer arithmetic algorithms and hardware designs”.
[13] ARM Architecture Reference Manual ARM Limited.
[14] ARM7TDMI Data Sheet ARM Limited.
[15] D. Pan. “A tutorial on MPEG/audio compression”, IEEE Multimedia, Vol. 2, No. 2, Summer 1995.
[16] http://ccrma.stanford.edu/CCRMA/Courses/422/projects/WaveFormat/
[17] K. Brandenburg and H. Popp. “An introduction to MPEG Layer-3”, EBU technical review, June 2000.
[18] Andreas Ehliar, Johan Eilert, “A hardware MP3 decoder with low precision floating point intermediate storage”, 2003
[19] http://documents.wolfram.com/applications/digitalimage/UsersGuide/8.6.html
[20] Ye-Xuan Yan, ... "A Field Programmable DSP Platform Design," Proceedings of the 2004 VLSI Design/CAD Symposium, 2004

校內：立即公開
校外：2005-07-28公開

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