低功率IC設計的議題越來越受到業界的重視。隨著製程演進，使得電路漏電流 ( Leakage current ) 呈現指數型的成長。因此現今工業界普遍採取的策略，是將IC設計分成不同電源域 ( Power domain )，並且在考慮低功率的電源域插入電源開關器 ( Power switch ) 以節省漏電流。由於電源開關器插入的數量以及擺置的位置，會影響整體晶片的面積和低功率電源域的電壓下降值，因此必須要有好好規劃。相對之前提出的方法[6][10][12]多半使用貪婪演算法(greedy algorithm) 直接決定電源開關器的位置和數量，本篇論文提出了一個有系統的方式來處理這個問題。我們首先決定電源開關器總等效電阻值，再配合整數線性規劃(Integer linear programming )和遞迴切割方法，來決電源開關器的數量和位置。最後，我們還利用二分逼近法[8]去逼近較佳的電源開關器總等效電阻值，此方法相較之前使用的方法具有更高的彈性，它可以針對不同的電源開關器型號來做選擇，並且可以在使用較少電源開關器面積需求去滿足設計者對於電壓下降的需求。實驗結果證明，根據實際業界提供的電路，貪婪演算法(greedy algorithm) 比我們的方法需要多9.7%的電源開關器總面積才能滿足電壓下降的限制。

Low-power IC design has attracted more attention recently. As advance in the manufacture process, leakage current grows exponentially. Hence, dividing IC design into several power domains and inserting power switches into low-power domains is a widely applied strategy to resolve the problem. Since insertion of the power switches has a great impact on the total area and IR-drop in low-power domains, a proper methodology is required. Relative to the previous methods [6][10][12] which determine number and locations of the power switches directly by greedy algorithms, this paper proposes a systematic methodology to handle this problem. Our approach first determines the equivalent resistance of required power switches in a low power domain, and then use integer linear programming and recursively partition based approach to determine the number and locations of power switches. Moreover, we use binary search method to find proper equivalent resistance of power switches, and this approach is more elastic and efficient than the previous methods, which is capable to fulfill designer’s IR-drop constraint using less power switch area. Experiment result demonstrates greedy algorithm requires at most 9.7% power switch area comparing to our approach under identical IR-drop constraint.

[1] M. Anis, S. Areibi, M. Mahmoud and M. Elmasry, “Dynamic and leakage lower reduction in MTCMOS circuits using an automated efficient gate clustering,” Proc. DAC, 2002, pp. 480-485.
[2] T. W. Chang, T. T. Hwang, and S. Y. Hsu, “Functionality directed clustering for low power MTCMOS design,” Proc. ASP-DAC, 2005, pp. 862-867.
[3] S. H. Chen, Y. L. Lin, M. and C. -T. Chao, “Power-up sequence control for MTCMOS designs,” IEEE Transactions on VLSI, Vol. 21, no. 3, pp. 413-423, 2013.
[4] H. Jiang, M. M. Sadowska, and S. Nassif, “Benefits and cost of power-gating technique,” Proc. ICCD, 2005, pp. 559-566.
[5] V. Khandelwal, and A. Srivastava, “Leakage control through fine-grained placement and sizing of sleep transistors,” Proc. ICCAD, 2004, pp. 533-536.
[6] J. N. Kozhaya, and L. A. Bakir, “An electrically robust method for placing power gating switches in voltage islands,” Proc. CICC, 2004, pp. 321-324.
[7] Z. Li, Y. Ma, Q. Zhou, Y. Cai, Y. Wang, T. Huang, and Y. Xie, “Thermal-aware power network design for IR drop reduction in 3D ICs,” Proc. ASP-DAC, 2012, pp.47-52.
[8] S. Sartaj, Data structures, Algorithms, and Applications in C++.McGraw2-Hill. 1998. ISBN 978-0072362268.
[9] K. Shi, Z. Lin, and Y. M. Jiang, “A power network synthesis method for industrial power gating designs,” Proc. ISQED, 2007, pp. 362-367.
[10] K. Shi, Z. Lin, Y. M. Jian, and L. Yuan, “Simultaneous sleep transistor insertion and power network synthesis for industrial power gating designs,” Journal of Computer, Vol.3, No.3, March 2008.
[11] T. M. Tseng, M. C.-T. Chao, C. P. Lu, and C. H. Lo, “Power-switch routing for coarse-grain MTCMOS technologies,” Proc. ICCAD, 2009, pp. 39-46.
[12] L. K. Yong, and C. K. Ung, “Power density aware power gate placement optimization scheme,” Proc. ASQED, 2010, pp. 38-42.
[13] Gate-level power analysis http://www.nspark.org.tw/webfiles/Power_Analysis.pdf
[14] http://www.synopsys.com/home.aspx
[15] http://www.globalfoundries.com