本研究設計與實作共享記憶體多處理器架構下可攜對稱式訊息傳遞與管理機制，提供符合此架構的平台之核心上運行行程可使用此機制達成核心間訊息交換。此外，針對可攜性來說，對於符合此架構的平台間之差異性，本研究將這些差異性參數化並設計與實作目標平台硬體環境配置介面程式，此介面主要提供符合架構的平台上一些相關參數可讓使用者根據其運行平台填寫相應參數並輸出硬體環境配置檔，如此可讓開發者更方便且有效率地產生符合其目標平台之對稱式訊息傳遞與管理機制。
為了提升使用本研究提出之對稱式訊息傳遞與管理機制的開發者發展更複雜、更多樣性應用之效率。本對稱式訊息傳遞與管理機制除了提供同步與非同步收送訊息之功能，亦提供跨核心行程協同合作之功能包含：接收特定核心行程訊息，查詢非同步傳遞之訊息後續狀態等服務。針對因使用同步收送訊息而陷入無窮等待的行程，則提供行程無窮等待處理機制，以及使用對稱式訊息傳遞與管理機制之服務訊息回報機制。
本研究之設計與實作於PAC DUO與OMAP35x平台驗證其可攜性。PAC DUO為三核系統晶片(SOC)，包含ARM處理器核心及兩顆工研院自行開發的DSP處理器核心，並提供核心間硬體溝通媒介之硬體郵箱(MailBox)機制。OMAP35x為雙核心系統晶片(SOC)，包含ARM處理器核心與DSP處理器核心，所提供的核心間硬體溝通媒介為共享記憶體搭配核心間硬體中斷。經實測結果，此兩平台核心上運行之行程，皆可使用本研究設計與實作之對稱式訊息傳遞與管理機制來達成核心間行程訊息交換，亦即證明本研究設計與實作之對稱式訊息傳遞與管理機制功能正確且具可攜性。

SUMMARY
Multi-processor or multi-core architecture has become a common feature in modern embedded system products. While the architecture helps improve system performance, one very important issue that can not be overlooked is the inter-process communication (IPC) which concerns processes running on the same processor as well as running on different processors. In this study, a portable symmetric message passing and management mechanism suitable for shared memory multi-processor architecture is designed and implemented. The main goal is supporting message exchange across processor cores in various contexts while achieving portability among shared memory multi-processor or multi-core platforms of similar architectures but equipped different IPC mechanisms so that cross-processor synchronization and co-operation between processes can be realized.
The symmetric message passing and management mechanism provides not only essential functionality of sending and receiving messages in both synchronous and asynchronous manners, but also supports functions of receiving message from specific processor core or process, querying the subsequent status of message asynchronously sent, and returning status code of function invocation. Regarding the issue that process might be trapped in the state of endless waiting due to sending or receiving message synchronously, a handling mechanism based on the concept of time-limit is provided. To address the portability issue, the differences in hardware IPC commonly available in multi-core platforms are analyzed and considered their characteristics as the parameters needed in building the binary executable for a platform. A user-friendly configuration program is implemented to help enter the platform-specific parameters when building the binary executable to run on a particular platform.
PAC DUO and OMAP35x shared memory multi-core platforms are used to conduct experiments in verifying the functionality and portability of this design and implementation. The experiment results show that all processes running on the two platforms can make use of this symmetric message passing and management mechanism for exchanging messages across processor cores, and prove the correctness of the functionality. Further, the binary executables for these platforms were built using the configuration program during conducting the experiments. Therefore, those results of the experiments also demonstrate the portability.
Key words: Shared Memory Multi-Processor Architecture, Symmetric Message Passing and Management Mechanism, Portability, PAC Duo, OMAP35x
INTRODUCTION
Multi-processor or multi-core architecture has become a common feature in modern embedded system products. The trend is deploying SOC (System-On-a-Chip) as the main hardware component in which two or more processor cores, which are not necessarily of the same type, are put into one single silicon chip. OMAP and DaVinci are well-known examples and both are composed of an ARM9 core and a DSP (Digital Signal Processing) core to form a platform of chip-level heterogeneous multi- processor architecture. Typically, the platform consists of one GPP (General Purpose Processor) and one or more SPP (Special purpose Processor) to co-operate, in addition to performing their dedicated functions. Such a configuration of multiple processor cores has been used in many consumer embedded system products.
While embedded system products based on multi-processor or multi-core architecture can effectively meet the requirements imposed from some possibly conflicting restrictions, such as high performance and low cost, the architecture of chip-level heterogeneous multi-processor not only brings new challenges but also increases complexity in developing embedded software. One very important issue that can not be overlooked is the inter-process communication (IPC) which concerns processes running on the same processor as well as running on different processors. The general requirement is that processes can communicate through exchanging messages or sharing data. In this study, a portable symmetric message passing and management mechanism suitable for shared memory multi-processor architecture is designed and implemented. The main goal is supporting application process to exchange messages across processor cores in various contexts while achieving portability among shared memory multi-processor or multi-core platforms of similar architectures but equipped different IPC mechanisms in order to help realize cross- processor synchronization and co-operation between processes.
The symmetric message passing and management mechanism consists of four main components in addition to the desirable hardware IPC supports, namely process communication manager, message queue manager, message exchanging interface function module, and the configuration program. In supporting exchanging messages across processor cores, it provides not only essential functionality of sending and receiving messages in both synchronous and asynchronous manners, but also supports functions of receiving message from specific processor core or process, querying the status of an asynchronously sent message, and returning status code of function invocation. In case that process might be blocked and trapped in the state of endless waiting due to sending or receiving message synchronously, a handling mechanism based on the concept of time-limit is provided.
The shared memory multi-processor architecture considered in this study mainly, but not necessarily, are heterogeneous multi-processor or multi-core architecture in which at least both shared memory of UMA (Uniform Memory Access) and hardware IPC mechanism are supported. The hardware IPC mechanism might be either simple inter-processor interrupt or inter-processor interrupt with mailbox capability. To achieve portability among these platforms, the hardware IPC mechanisms are analyzed and the platform-specific characteristics data can be entered through the configuration program when building the binary executable to run on a particular platform.
Based on the design and implementation of the symmetric message passing and management mechanism, PAC DUO and OMAP35x shared memory multi-core platforms are used to conduct experiments in order to verify its functional correctness and portability. The binary executables for these platforms were built using the configuration program to enter platform-specific data values. The results from these experiments show that all processes running on the two platforms can make use of this symmetric message passing and management mechanism for exchanging messages across processor cores, and hence prove the correctness and portability.

MATERIALS AND METHODS
The symmetric message passing and management mechanism is designed with the assumption that the multi-processor or multi-core platform supports shared memory and hardware inter-processor interrupt as the hardware components of the mechanism. The hardware inter-processor interrupt may have mailbox capability which enables the interrupt signal to carry a short message of command and limited amount of data for cross-processor communication. In case of an inter-processor interrupt without mailbox capability, a small amount of the shared memory is allocated for the purpose of mailbox instead. The software part of the mechanism is designed to have four components, namely communication manager, message queue manager, message exchanging interface function module, and a configuration program. The names imply their functionality and Table 1 lists the message exchange functions in the module which are invoked by applications to deliver messages.
Based on the purposes, there are messages for the communication between the communication managers and the messages of application processes. All the message exchanges are handled by the communication manager deployed at each processor core while application processes request communication manger to deliver messages by invoking a suitable message exchange interface function. To prevent a process from waiting endlessly due to using blocking message exchange functions, such as blocked sending, blocked receiving, and send-and-wait-response, the communication manager is designed to check for such cases when it is running. Each waiting is associated with an attribute of time-limit so that the communication manager can intervene to abort the waiting after a long enough time has elapsed.
The configuration program plays the role of achieving portability. It is designed to help enter platform-specific data values of hardware parameters in order to build the binary executable of the communication manager. The parameters, such as the presence of hardware mailbox and the I/O address of inter-processor interrupt, are obtained via analyzing the hardware features essential to the implementation of the mechanism. This configuration program produces a header file to be included as part of the source program code of the communication manager.
RESULTS AND DISCUSSION
TI’s heterogeneous multi-core platform OMAP35x and ITRI’s heterogeneous multi-core platform PAC DUO are employed for functional and Portability testing in the present paper. The functional test is divided into two parts, namely user call function such as: query send, non-blocking receive, send and wait and send response; and underlying features of Symmetric message passing and management mechanism, such as: IPC Manager, message queue storage and management mechanism, handling mechanism for endless wait of processes and message return mechanisms for functional testing. Regarding Portability verification, output configuration files from an interface program for user development platform hardware environment configuration provided in the present paper after setting corresponding parameters, compile them respectively to generate corresponding executable files, and load them into PAC DUO and OMAP35x for the aforementioned functional testing. The final test results show that the processes running on the two platforms can exchange messages between cores in accordance with the functions designed in the present paper, which proves the feasibility and Portability of the mechanism proposed in the present paper.
CONCLUSIONS
The design of this portable symmetric message passing and management mechanism is implemented using C programming language for Linux operating system and C/OS-II real-time kernel. It is tested for functional correctness and portability by the experiments using two shared memory multi-core platforms, namely PAC DUO and OMAP35x. PAC DUO is a triple-core SOC which contains one ARM processor core and two DSP processor cores developed by ITRI and provides hardware mailbox mechanism as the communication media between the processor cores. OMAP35x is a dual-core SOC of an ARM processor core and a DSP processor core, which is one of the popular embedded system platform products of Texas Instruments and provides shared memory and hardware inter-processor interrupts as the communication media between processor cores.
While the portability can be demonstrated through entering platform-specific data values using the configuration program and building the binary executable, the experiments of functional tests are divided into two groups: the message exchanging function tests and the management function tests. The former includes invoking cross-processor message transmission functions from applications, such as functions of non-blocking send and receive, blocking send and receive, query send, send and wait, send response. The later includes handling message exchanges between the communication managers on both sides of the hardware IPC mechanism and handling potentially endless waiting of application processes, in addition to the management functions in delivering messages to applications. All the results from the experiments are satisfactory and thus prove the functional correctness as well as the portability.

[1] Abraham Silberschatz, Greg Gagne, Peter Baer Galvin, “Operating System Concepts”, 8th edition, Wiley, August 2008, ISBN 978-0-470-12872-5.
[2] Andrew Stuart Tanenbaum, “Modern Operating Systems”, 2nd edition, Prentice Hall, March 2001, ISBN 978-986-7790-93-4.
[3] Andrew Stuart Tanenbaum, “Structured Computer Organization”, 5th edition, Prentice Hall, June 2005, ISBN 978-0-13-148521-1.
[4] ARM, “ARM11 MPCore Processor Technical Reference Manual”, Revision: r2p0, ARM Doc. No. DDI-0360F, 2008.
[5] ARM, “ARM11MPCore Processor”,
http://www.arm.com/products/processors/classic/arm11/arm11-mpcore.php, August 2013.
[6] ARM, “Cortex-A9 MPCore Technical Reference Manual”, Revision: r2p0, ARM Doc. No. DDI-0407E, 2009.
[7] Beej Jorgensen, “Beej's Guide to Unix IPC”
http://beej.us/guide/bgipc/output/html/singlepage/bgipc.html, June 2013.
[8] David J Greaves, “System on Chip Design and Mo delling”, Computer Laboratory, University of Cambridge,
http://www.cl.cam.ac.uk/teaching/0910/SysOnChip/socdam-notes1011.pdf, 2011.
[9] Edgar Knapp, “Deadlock Detection in Distributed Databases”, Communications of ACM, Vol.19, issue 4, pp. 304-328, December 1987.
[10] Garen Ken, “Software Portability: Weighing Options, Making Choices”, The CPA Journal, Vol. 77, No. 11, November 2007.
[11] Guan-Ying Huang, “The Design and Implementation of Symmetric Message Passing and Massagement Mechanism in Heterogeneous Multi-Core Architecture”, Master Thesis, Instiute of Computer and Communication Engineering, National Cheng Kung University, July 2010.
[12] ISA Lab.,“Distributed Deadlock Detection”,
http://203.250.33.57/dos/ch8.pdf, August 2013.
[13] ITRI, “PAC DUO Embedded OS Setup GUIDE V2.2”, 2011.
[14] ITRI, “PAC Duo Programming’s Reference Guide”, 2009.
[15] ITRI, “PAC Duo SoC Mailbox User Guide”, 2010.
[16] ITRI, “PAC Duo SoC Specification”, 2011.
[17] ITRI, “PACDSP V3 Compiler User Guide”, 2008.
[18] James D. Mooney, “Bringing Portability to the Software Process”, Technical Report TR 97-1, West Virginia University, Dept. of Statistics and Computer Science, 1997.
[19] K. Mani Chandy, Jayadev Misra, Laura M. Haas, “Distributed Deadlock Detection”, Communications of the ACM, Vol.1, issue 2, pp.144-156, May 1983.
[20] Mistral Solutions, “OMAP35x Evaluation Module Hardware User Guide”, Rev. 1.5 21, September 2009.
[21] MSDN, “Interprocess Communications”,
http://msdn.microsoft.com/en-us/library/windows/desktop/aa365574(v=vs.85).aspx, August 2013.
[22] Mukesh Singhal,” Deadlock Detection in Distributed System”, Communications of Computer, Vol.22, issue 11, p.37-48, November 1989.
[23] Neil Matthew, Richard Stones, “Beginning Linux Programming”, 4th edition, Wiley, October 2008, ISBN 978-986-181-549-7.
[24] Omappedia, “DSPBridge Project”,
http://www.omappedia.org/wiki/DSPBridge_Project57, Auguest 2013.
[25] Paul Krzyzanowski, “Distributed Deadlock”,
https://www.cs.rutgers.edu/~pxk/417/notes/deadlock.pdf, October 2012.
[26] Pei-Yu Li, “The Formal Description of Resource Deadlock in Distributed Systems”, Unpublished Doctoral Dissertation, University of Missouri, Rolla, Missouri, 1994.
[27] Saeed K. Rahimi, Frank S. Haug, “Distributed Database Management Systems: A Practical Approach”, 1st edition, Wiley, August 2010, ISBN 978-0-470-40745-5.
[28] Scott M. Lewandowski, “Interprocess Communication in UNIX and Windows NT”, Department of Computer Science, Brown University,
http://cs.brown.edu/~scl/files/IPCWinNTUNIX.pdf, 1997
[29] Sudeep Pasricha, Nikil Dutt, “On-Chip Communication Architectures: System on Chip Interconnect”, 1st edition, Morgan Kaufmann, May 2008, ISBN 978-0-12-373892-9.
[30] Sven Goldt, Sven van der Meer, Scott Burkett, Matt Welsh, “The Linux Programmer’s Guide”,
http://jasonscalia.com/LDP/LDP/lpg-0.4.pdf, March 1995.
[31] Texas Instruments, “DSP Bridge Application Integration Guide3430”, 2006.
[32] Texas Instruments, “OMAP35x Applications Processor Technical Reference Manual”, Literature Number: SPRUF98X, June 2012.
[33] Texas Instruments, “OMAP5910 Dual-Core Processor Data Manual”, Literature Number: SPRS197D, August 2004.
[34] Texas Instruments, “OMAP5910 Dual-Core Processor Technical Reference Manual”, Literature Number: SPRU602B, January 2003.
[35] Texas Instruments, “Programming Guide for DSP/BIOS™ Bridge”, 2008.
[36] Texas Instruments, “TMS320DSC25 DSP Technical Reference Manual”, 2001.
[37] Wikipedia, “Windows 8”, http://zh.wikipedia.org/wiki/Windows_8.
[38] Wikipedia, “μC/OS-II”, http://en.wikipedia.org/wiki/MicroC/OS-II.