本篇論文提出一個高產出率低面積的離散餘弦轉換架構，此架構能應用於H..264的高解析度視訊產品。在H.264中，離散餘弦轉換的區塊大小為4乘4以及8乘8，其中8乘8區塊大小的離散餘弦轉換主要應用於標準解析度與高解析度以及更高解析度的視訊上。本篇論文即為實現8乘8區塊大小離散餘弦轉換的架構。為了能用於高解析度視訊，此架構必須能有足夠高的產出率。但高產出率常伴隨面積較大的問題，因此本篇論文利用部分離散餘弦轉換的特性使面積下降。以此完成高產出率低面積的架構。
本篇論文提出的架構所支援的規格為1080p與每秒60幀數。此架構利用tsmc.18μm的製程規格來進行邏輯電路合成，操作的時脈為81百萬赫茲。在此時脈下本篇論文所提出的架構可以以與類似架構相較之下，較小的面積來完成H.264 8×8 離散餘弦轉換的架構。

This thesis proposes a Discrete Cosine Transform architecture with high throughput and low area. This architecture can be applied in H.264 High Definition (HD) resolution video products. In H.264, the block sizes of the Discrete Cosine Transform are 4×4 and 8×8. The 8×8 block size transform is mainly used in Standard Definition resolution, High Definition resolution, and above Definition resolution. This thesis implements an 8×8 transform architecture. For application in HD resolution video products, the proposed architecture supplies enough high throughput, but a big area should also be associated with a high throughput. Through some property of the DCT, this thesis shows that the area can be reduced and then a high
throughput and small area architecture can be implemented.
In the proposed architecture, the specification of proposed architecture is 1080p and 60 frames per second. The proposed architecture is synthesized with
TSMC 0.18 μm technology cell library and the operating speed is 81 MHz. In this operation speed, the proposed architecture has smaller area when compared with other
architectures which also implement H.264 8×8 DCT architecture recently.

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