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研究生： 蘇鈺雄
Su, Yu-Hsiung
論文名稱： 適用於三維晶片以矩陣摺積技術為主之電子系統層級高效溫度模擬器
A highly effective transient thermal simulator using matrix convolution at Electronic System Level for three-dimensional integrated circuits
指導教授： 邱瀝毅
Chiou, Lih-Yih
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2014
畢業學年度： 103
語文別： 英文
論文頁數： 48
中文關鍵詞： 溫度模擬器 、矩陣摺積 、三維晶片 、暫態分析
外文關鍵詞： thermal simulator, matrix convolution, three-dimensional integrated circuits, transient analysis, power blurring
相關次數： 點閱：134  下載：0 
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    • 隨著整體製程的微縮以及系統上對功能要求的提高，在晶片上的功率消耗與隨之而來的熱也不斷地增加。半導體晶片對熱的忍受度是有限的，若有過度的熱在晶片上會導致系統功能故障、可靠度降低、壽命減短、消耗功率增加等副作用。單純只依靠封裝技術散熱會增加晶片的成本百分之二十至八十不等。因此在設計時必須要利用溫度模擬器來考量晶片的受熱狀況。一個好的溫度模擬器必須盡量滿足模型建構快、可重複使用模型、支援不同系統架構與封裝、執行速度快等各種條件。另外對於現今運作頻率越來越高的晶片，傳統上所使用的穩態分析已經不足以反映現實環境在時間與空間上的快速變化。為了解決以上所提的各種問題，本論文致力於打造一個以矩陣摺積技術為主之高效溫度模擬器，支援最新的三維晶片設計技術與暫態分析，並在電子系統層級上實作以期與更多相關技術與平台連結。

    As technology shrinks and performance requirement raises, power consumption creates great amount of heat. Excessive heat causes function failure, reliability downgrade and other side effects. Chip cost increases by 20~80% if only package and assembly are considered for maintaining normal temperature under severe thermal circumstances. Thermal-aware designs require thermal simulators to accurately predict temperature distribution on chip before tapeout. An ideal thermal simulator builds models fast and efficiently, support different architecture and package with short execution time. Nevertheless, faster operational frequency made traditional steady-state analysis inadequate for simulating real world circumstances. This work devoted to build a highly effective transient thermal simulator using matrix convolution at Electronic System Level. Proposed simulator applies thermal-aware transient power blurring algorithm save 99% of execution time against ANSYS ICEPAK with only 4% error and extend power blurring to three-dimension analysis.

    摘 要 i Abstract ii 誌 謝 iii Contents iv List of Tables vii List of Figures viii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Background 3 1.2.1 Thermal simulators 3 1.2.2 Early thermal evaluation 5 1.2.3 Supporting different architecture 5 1.2.4 Collaboration with other models 5 1.2.5 Transient / Steady-state analysis 6 1.3 Problem description 6 1.4 Contributions 7 1.5 Organization of thesis 7 Chapter 2 Related Works 8 2.1 Thermal models 8 2.1.1 Finite Difference Method/Finite Element Method 8 2.1.2 Thermal RC 10 2.2 Matrix convolution based technique 11 2.2.1 Power blurring 11 2.2.2 Convolution by Image 12 2.2.3 Intrinsic error 13 2.2.4 Temperature variation 14 2.2.5 Look-up table based method 15 2.3 Three-dimensional integrated circuits 15 2.3.1 Multiple active layers 16 2.3.2 Through Silicon Via (TSV) 16 Chapter 3 Proposed Method 18 3.1 Problem description 18 3.2 Mask construction 19 3.3 Transient analysis 20 3.4 Convolution 21 3.5 Thermal related issues 21 3.5.1 Conduction 22 3.5.2 Convection 22 3.6 3D issue 22 3.7 Algorithm of the simulator 23 3.8 Pseudo code of the thermal simulator 25 Chapter 4 Experimental Results and Analysis 27 4.1 General experimental setup 27 4.1.1 Test cases 27 4.1.2 Meshing conditions 28 4.1.3 Error calculation 29 4.2 Transient analysis 29 4.2.1 Experimental environment and setup 30 4.2.2 Validation flow 30 4.2.3 Transient simulation 30 4.3 Conduction analysis 32 4.3.1 Experimental environment and setup 32 4.3.2 Validation flow 32 4.3.3 Conduction effect 32 4.4 Convection analysis 33 4.4.1 Experimental environment and setup 34 4.4.2 Mask adaption for different temperature 34 4.5 Transient analysis 35 4.5.1 Experimental environment and setup 35 4.5.2 Error analysis 35 4.6 3D simulation 36 4.6.1 Experimental environment and setup 36 4.6.2 Stacked structure 37 4.7 Mask size analysis 38 4.7.1 Experimental environment and setup 38 4.7.2 Mask size trade-off 38 4.8 Speed analysis and memory analysis 40 4.8.1 Experimental environment and setup 40 4.8.2 Speed analysis 41 4.8.3 Memory usage analysis 41 Chapter 5 Conclusion and Future Works 43 5.1 Conclusion of this work 43 5.2 Future works 43 5.2.1 Real world validation 43 5.2.2 Radiation effect 44 5.2.3 Fast matrix convolution 44 5.2.4 Three-dimensional ICs 44 References 45 個人簡歷 48

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