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研究生：	林宇浩 Lin, Yu-Hao
論文名稱：	使用新型二元搜尋演算法之全數位延遲鎖定迴路 An All-Digital Delay-Locked Loop by Using a New Binary Search Algorithm
指導教授：	賴源泰 Lai, Yen-Tai
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2010
畢業學年度：	98
語文別：	英文
論文頁數：	79
中文關鍵詞：	延遲鎖定、二元搜尋演算法
外文關鍵詞：	Delay-Locked Loop, Binary Search Algorithm
相關次數：	點閱：60 下載：0
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隨著超大型積體電路製程的進步，電路執行速度以及效能也隨之增加，因此，許多在於強調時脈同步、減少時脈歪斜及資料連結的技術被提出來處理上述問題，例如延遲鎖定迴路(Delay-Locked Loop)及延遲鎖相迴路(Phase-Locked Loop)，由於延遲鎖定迴路提供無條件穩定、無相位誤差累積、快速鎖定、低抖動等優點，所以延遲鎖定迴路被更廣為運用於數位系統介面。其中全數位延遲鎖定迴路相較於傳統類比式延遲鎖定迴路更具有抗雜訊、與電路整合度高、更快速的鎖定時間、較容易設計等優點。本論文中，我們針對全數位連續近似暫存器延遲鎖定迴路提出了一個新的二元搜尋演算法，將傳統連續近似暫存器延遲鎖定迴路在漸進式遞增延遲線長度過程中所產生諧波鎖定以及重複搜索的問題移除外，並將二元搜尋的概念運用於延遲線搜索的過程中，可以降低搜索時間以達到鎖定狀態

本論文設計使用台積電0.18μm 1P6M CMOS 製程製作，操作頻率從55MHz到500MHz，在最高頻率操作下量測到的功率消耗為10.2mW，操作頻率為500MHz時的方均根抖動值為2.15ps。

For the rapid progress of VLSI process technology, the developed VLSI systems nowadays have features of ultra-high operation speed and performance. Thus, a lot of technologies such as Delay-Locked Loops (DLLs) and Phase-Locked Loops (PLLs) have been developed to handle the problems of clock synchronization, clock deskew buffer and data link. The all-digital type DLLs have good performance in the tolerance of noise, the capability of integration, and fast locking time. In this paper, we proposed an all-digital DLL by using a new binary search algorithm. The drawback of redundant repetitive searches is removed in this work. Moreover, the concept of binary search algorithm is also adopted to speed the locking process.
This work is fabricated in TSMC 0.18μm 1P6M CMOS process. The operation frequency ranges from 55MHz to 500MHz. The power consumption is 10.2mW and r.m.s jitter is 2.15ps at 500MHz input clock frequency.

ABSTRACT
CONTENTS
LIST OF TABLES
LIST OF FIGURES
Chapter 1 Introduction........................1
1   Motivation..............................1
2   Introduction of Clock Skew..............2
3   Thesis Overview.........................4
Chapter 2 Delay-Locked Loop...................5
1   Introduction............................5
2   Basic of Delay-Locked Loops.............6
2.1  Introduction...........................6
2.2  PD (Phase Detector)....................8
2.3  CP (Charge Pump) / LF (Loop Filter)....9
2.4  Voltage-controlled delay line..........10
2.4.1  RC Time Constant Delay Cell..........11
2.4.2  Current-Starved Delay Cell...........12
3   Stability Analysis......................13
4   Design Consideration of DLLs............15
Chapter 3 Characteristics of Digital Delay-Locked Loop...19
1   Design of Conventional Digital DLL......20
2   Register-Based DLL......................21
3   Counter-Based DLL.......................23
4   Successive Approximation Register-Controlled DLL...25
4.1   Conventional SAR DLL..................25
4.2   Variable SAR DLL......................27
5   Digitally Controlled Delay Line.........30
5.1   Coarse-Tuning Delay Cell..............31
5.2   Fine-Tuning Delay Cell................33
6   Comparisons of Digital DLL and Analog DLL..........35
Chapter 4  All-Digital Delay Lock Loop Using a New Binary Search algorithm.........................................37
1  Repetitive Search Issue of Variable SAR Algorithm...37
2  System Architecture.................................40
2.1  Fast-Locking Variable SAR algorithm...............40
2.2  Recursive SAR algorithm...........................45
2.3  Simulink Simulation results.......................48
3  Circuit Implementations.............................53
3.1  True Single Phase Clock (TSPC)DFF.......................53
3.2  FVSAR and RSAR Controllers........................54
3.3  Fail-to-Lock Judgment Circuits....................60
3.4  Digital-Controlled Delay Line.....................62
3.5  Phase Detector....................................66
Chapter 5  Experimental Results and Conclusions..........68
1   Experimental Results...............................68
2   Conclusions........................................75
REFERENCES...............................................76	

                                    

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校內：2020-07-20公開
校外：不公開電子論文尚未授權公開，紙本請查館藏目錄

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