為了因應多元化的使用需求，整合多種應用如H.264、MPEG等多媒體壓縮技術於同一晶片與多格式矽智財（IP）的開發越來越被重視。在以匯流排通訊架構為主的設計中，矽智財間的資料傳輸與溝通將會成為影響整體效能與功率消耗的關鍵。我們運用多目標基因演算法提出了一個可同時考量多種模式的快速匯流排通訊架構探勘方式，提出的演算法不僅可以考量各個模式的執行效能，也能進行功率消耗的最佳化。在實驗結果中，提出的演算法可找到的匯流排通訊架構離全域最佳解只有7％差距，同時也增快了多模式在利用基因演算法進行匯流排架構探勘時的效率，不必犧牲解的品質就能減少至多59％的探勘時間。

Integrating various applications such as H.264, MPEG etc. into a chip and forming to a multi-mode IP are increasingly important for meeting versatile consumers’ demands. In bus-based design, data transfer among the communication architecture may become the bottleneck of system performance and power consumption. We proposed an efficient bus-based communication architecture exploration method for a multi-mode system using a multi-objective genetic algorithm. The proposed method can explore communication architectures that not only meet performance constraints for all modes but also optimize the power on system communication. Experimental results indicate the proposed method is close to the optimal solution within 7%, we also overcome the inefficient searching in the genetic algorithm and obtain time improvement by up to 59% without compromising the quality of the solution.

[1] C. Ju, T. Liu, Y. Chang, C. Wang, H. Lin, S. Cheng, C. Chen, F. Chiu, K. Lin, C. Wu, S. Liang, S. Wang, G. Chen, T. Hsiao, and C. Wang, “A 125Mpixels/sec full-HD MPEG-2/H.264/VC-1 video decoder for Blu-ray applications,” IEEE Asian Solid-State Circuits Conference, 2008, pp. 9-12.
[2] H. Mizosoe, D. Yoshida, and T. Nakamura, “A Single Chip H.264/AVC HDTV Encoder/Decoder/Transcoder System LSI,” IEEE Trans. on Consumer Electronics, vol.53, pp. 630-635, 2007.
[3] J. Zheng, W. Gao, D. Wu, and D. Xie, “A novel VLSI architecture of motion compensation for multiple standards,” IEEE Trans. on Consumer Electronics, vol.54, pp. 687-694, 2008.
[4] S. Lee and K. Cho, “Circuit implementation for transform and quantization operations of H.264/MPEG-4/VC-1 video decoder,” International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2007, pp. 102-107.
[5] K. Lahiri, A. Raghunathan, and S. Dey, “Design space exploration for optimizing on-chip communication architectures,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol.23, pp. 952-961, 2004.
[6] G. Chandra, P. Kapur, and K. Saraswat, “Scaling trends for the on chip power dissipation,” in Proc. of the IEEE 2002 International Interconnect Technology Conference, 2002, pp. 170-172.
[7] K. Lahiri and A. Raghunathan, “Power analysis of system-level on-chip communication architectures,” International Conference on Hardware/Software Codesign and System Synthesis, 2004, pp. 236-241.
[8] S. Pasricha, N. Dutt, and M. Ben-Romdhane, “Automated throughput-driven synthesis of bus-based communication architectures,” in Proc. of the Asia and South Pacific Design Automation Conference, 2005, pp. 495-498 Vol. 1.
[9] T.C Kuo, “Power and Performance Exploration for System-Level Communication Architecture Using Trace-Driven Approach,” in Department of Electrical Engineering Thesis for Master of Science National Cheng-Kung University , Tainan, Taiwan, Jul. 2007.
[10] P. Lieverse, P.V.D. Wolf, K. Vissers, and E. Deprettere, “A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems,” J. VLSI Signal Processing System, vol.29, pp. 197-207, 2001.
[11] T. Givargis, F. Vahid, J. Henkel, and S. Member, “Evaluating Power Consumption of Parameterized Cache and Bus Architectures in System-on-a-Chip Designs,” IEEE Trans. on VLSI Systems, vol.9, pp. 500-508, 2001.
[12] N.S. Voros and K. Masselos, “Reconfiguable Hardware Exploitation in Wireless Multimedia Communications,” System Level Design of Reconfigurable System-on-Chip, Springer, 2005.
[13] S. Srinivasan, L. Li, and N. Vijaykrishnan, “Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures,” in Proc. of the conference on Design, Automation and Test in Europe - Volume 1, 2005, pp. 218-223.
[14] C. Lee, “System Level Bus-Based Communication Architecture Exploration for Power and Performance Using Modified Simulated Annealing Algorithm,” in Department of Electrical Engineering Thesis for Master of Science National Cheng-Kung University , Tainan, Taiwan, Jun. 2008.
[15] M. Hase, K. Akie, M. Nobori, and K. Matsumoto, “Development of Low-power and Real-time VC-1/H.264/MPEG-4 Video Processing Hardware,” in Proc. of the 2007 conference on Asia South Pacific design automation, 2007, pp. 637-643.
[16] Y. Tsai, “Design of 2-D Inverse Transformation for Multiple-Standard Video Coding Applications and Its Prototype System,” in Department of Electrical Engineering Thesis for Master of Science National Cheng-Kung University , Tainan, Taiwan, Jun. 2008.
[17] H.G. Lee, N. Chang, U.Y. Ogras, and R. Marculescu, “On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches,” ACM Trans. Design Automation Electronic System, vol.12, pp. 1-20, 2007.
[18] H. Nakata, K. Hosogi, M. Ehama, T. Yuasa, T. Fujihira, K. Iwata, M. Kimura, F. Izuhara, S. Mochizuki, and M. Nobori, “Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architecture,” Asia and South Pacific Design Automation Conference, 2009, pp. 528-534.
[19] T. Liu, T. Lin, S. Wang, W. Lee, J. Yang, K. Hou, and C. Lee, “A 125 μW , Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications,” IEEE Journal of Solid-State Circuits, vol.42, pp. 161-169, 2007.
[20] R. Marler and J. Arora, “Survey of multi-objective optimization methods for engineering,” Structural and Multidisciplinary Optimization, vol.26, pp. 369-395, Apr. 2004.
[21] J.D. Schaffer, “Multiple Objective Optimization with Vector Evaluated Genetic Algorithms,” in Proc. of the 1st International Conference on Genetic Algorithms, 1985, pp. 93-100.
[22] J. Knowles and D. Corne, “The Pareto Archived Evolution Strategy: A New Baseline Algorithm for Pareto Multiobjective Optimisation,” in Proc. of the Congress on Evolutionary Computation, 1999, pp. 98-105.
[23] E. Zitzler and L. Thiele, “Multiobjective evolutionary algorithms : A comparative case study and the strength Pareto approach,” IEEE Trans. on Evolutionary Computation, pp. 257-271, 1999.
[24] N. Srinivas and K. Deb, “Multiobjective Optimization Using Nondominated Sorting in Genetic Algorithms,” IEEE Trans. on Evolutionary Computation, vol.2, pp. 221-248, 1994.
[25] K. Deb, A. Pratap, S. Agarwal, and T. Meyarivan, “A Fast Elitist Multi-Objective Genetic Algorithm: NSGA-II,” IEEE Trans. on Evolutionary Computation, vol.6, pp. 182-197, 2000.
[26] D. Goldberg and J. Richardson, “Genetic algorithms with sharing for multimodal function optimization,” in Proc. of the Second International Conference on Genetic Algorithms on Genetic algorithms and their application, 1987, pp. 41-49.
[27] J. Horn, N. Nafpliotis, and D.E. Goldberg, “A Niched Pareto Genetic Algorithm for Multiobjective Optimization,” in Proc. of the First IEEE Conference on Evolutionary Computation, vol.1, pp. 82-87, 1994.
[28] Z.M. Hsu, “Trace-driven system-level power estimation of communication architecture,” in Department of Electrical Engineering Thesis for Master of Science National Cheng-Kung University , Tainan, Taiwan, Jul. 2006.
[29] L.Y. Chiou and Y.S. Chen, “Performance Analysis for the Simultaneous Exploration,“ Department of Electrical Engineering, National Cheng-Kung University, Tainan, Taiwan (under preparation).
[30] S. Pasricha, N. Dutt, and M. Ben-Romdhane, “Extending the transaction level modeling approach for fast communication architecture exploration,” in Proc. of the 41st annual Design Automation Conference, San Diego, CA, 2004, pp. 113-118.
[31] K. Lahiri, A. Raghunathan, and S. Dey, “System-level performance analysis for designing on-chip communication architectures,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol.20, pp. 768-783, 2001.
[32] C. Hsieh and M. Pedram, “Architectural power optimization by bus splitting,” in Proc. of the conference on Design, automation and test in Europe, 2000, pp. 612-616.
[33] “AMBA AHB,” AMBA 2.0 Specification, ARM Inc., http://www.arm.com/products/solutions/AMBA_Spec.html.
[34] R. Dick, D. Rhodes, and W. Wolf, “TGFF: task graphs for free,” in Proc. of the Sixth International Workshop on Hardware/Software Codesign, 1998, pp. 97-101.
[35] M. Mahdi Ghandi and Mohammad Ghanbari, “The H.264/AVC Video Coding Standard for the Next Generation Multimedia Communication,” Iranian Association of Electrical and Electronics Engineers Journal, vol.1, pp. 3-14, 2004.
[36] K. Sastry, “Single and Multiobjective Genetic Algorithm Toolbox in C++,” Jun. 2007. http://www.illigal.uiuc.edu/pub/papers/IlliGALs/2007016.pdf