隨著百家齊鳴的消費電子商品趨向輕薄短小、具多功能性、高處理速度等等因素，晶片製造業者必須全力發展低成本、體積輕巧的整合封裝技術，同時加速新產品上市時間，以滿足市場需求。尤其是當整個代工晶圓片大小從六吋、八吋直到目前市場主流十二吋，製程能力從90奈米、65奈米、28奈米一直到7奈米，無疑是對生產成本，品質穩定的一大考驗。
當元件尺寸不斷縮小，單位面積元件數目越來越多的情況下，晶圓良率(Yield)也就越來越重要。對於晶圓的尺寸越做越大，隨之而來也就需要更多的技術挑戰，例如製程中均勻度的控制能力。隨著晶體結構上的調整，蝕刻技術能力的改良，卻也帶來更多難以控制的負面副產物(By-product)，造成晶圓整面的良率降低。而良率和售價是成正比，故晶圓代工的良率穩定提升，將是所有代工廠在目前產業獲利競爭中的重要研究之一。
本論文探討一上市晶圓代工廠的實際案例，觀察到可能產生的缺陷(Defect)來源，並加以分析之成因。當中針對機台參數設定，製程能力條件，來研判微觀電弧放電(Micro arcing)的現象是否改善。進而在缺陷尚未形成之前，使用一些技術手法，將其解決。
研究結果發現：同一種產品中經過射頻功率(Radio frequency power)調整以及除電技術處理過的晶圓，其晶圓缺陷確實比原蝕刻技術的來得低。以28奈米製程舉例來說，整體晶圓良率可以提升將進10%以上。
根據本實驗的結果，可預期的是，若將實驗結果應用於未來更先進的製程上，半導體代工廠的製程良率將可得到顯著的提升。

This thesis explores into the issues currently experienced by wafer foundry , observe the source of those possible defect and analyze the contributing elements. Among all, the setting of hardware configuration and the foundation of processing capability would be the key indicator in determining whether there’s improvement in micro arcing phenomenon. The priority is to utilize some technological methods to resolve those negative phenomenon prior to the forming of defects.

Key words: semiconductor production process/procedure, wafer foundry, back end of line (BEOL) etch, arcing analysis.

參考文獻
一. 中文部分
1. 胡恩德(2001)，「真空中直流電氣銀接點電弧特性和損耗形成機制之研究」，國立中山大學機械工程研究所碩士論文
2. 譚芳(2009)，「SIPOC模型在企業風險管理中的應用」，財會通訊，中國
二. 英文部分
1. Fu, M. S., Liu, M. C., Hsieh, M. S., Huang, C. C. and Kuo, S. W.(2002), Study of Wafer Arcing on Oxide Etching Process for Advance VLSI Technology, Semiconductor Manufacturing Technology Workshop, pp. 157-160
2. Fischer, Pirkle, D., Wu, D., Loewenhardt, P., Tietz, J. and Marks, J.(2002), Plasma Process Induced Damage Conference (Maui, HI), pp.130-133
3. Guldi, R., Winter, T., Sridhar, N., Smith, J., PapaRao, S., Garvin, J. and Metteer, B.(1999), Systematic and Random Defect Reduction During the Evolution of Integrated Circuit Techology, IEEE, pp.2-7
4. Ishikawa, K.(1968), Guide to Quality Control, JUSE, Tokyo
5. Lee, H. J., Hung, C. L., Leng, C. H., Lian, N. T., Young, L. W., Yang, T., Chen, K. C. and Lu, C. Y.(2008), Etch Defect Characterization and Reduction in Hard-Mask-Based Al Interconnect Etching
6. Lee, H. J., Wei, K. L., Lian, N. T., Yang, T., Chen, K. C. and Lu, C. Y.(2010), Reduction of Shorts between Word Lines on Charge-Trapping Flash Cell in a Self-Aligned Double Patterning Technology, IEEE, pp. 84-87
7. Lee, H. J., Lin, S. Y., Lin, I-T., Wei, K. L., Chang, S. Y., Lian, N. T., Yang, T., Chen, K. C. and Lu, C. Y.(2011), Post Etch Killer Defect Characterization and Reduction in a Self-Aligned Double Patterning Technology, IEEE, pp. 1-4
8. Lee, H. J., Yu, H. S., Lee, S. C., Yang, C. K., Chang, S. E., Lo, K. F., Lin, X. G., Lian, N. T., Yang, T. and Chen, K. C.(2015), A Case Study on Severe Yield Loss Caused by Wafer Arcing in BEOL Manufacturing, IEEE, pp. 132-162
9. Ma, S., Straube, R., Ou-Yang, E., Yu, J., Cheng, L., Dahimene, M. and Shan, H.(2001), Engineering and Technology Internal Conference (Santa Clara, CA, papar#605, session#4-F7
10. Ma, S., Hanabusa, N., Mays, B., Shoji, S., Detrick, T., Pattada, B., Kutney, M., Shin, N., Yang, J., Chou, R., Chen, B., Lu, A., KO, S., Yang, C., Li, D., Huang, J., Lin, V., Lo, A. and Yu, J.(2002), Engineering and Technology Internal Conference (Santa Clara, CA), paper#534
11. Ma, S., Hanabusa, N., Mays, B., Shoji, S., Kuyney, M., Detrick, T., Pattade, B. and Straube, R.(2003), Backend Dielectric Etch Induced Wafer Arcing Mechanism and Solution, IEEE, pp. 37-52,150-181