H.264/AVC在視訊多媒體方面扮演了很重要的角色，不管是在壓縮率和影像品質都明顯優於以往的視訊標準。而在H.264中，移動估測(motion estimation, ME)更成為了視訊編碼的核心，其中採用了多福參考畫面(multiple reference frames)、可變區塊大小的移動估測(variable block size motion estimation)、移動向量(motion vector)可搜尋至四分之ㄧ像素精確度(quarter pixel resolution) 等，都是為了要提高影像的品質和更精準的預測，但這也使得了移動估測的運算量與複雜度大幅的提升。
此篇論文將提出可變區塊大小移動估測之超大型積體電路架構應用於三步搜尋法。移動估測將以管線化設計並規劃成平行處理方式來增加資料產出量，在處理單元方面則利用計算小的區塊大小來組合出大的區塊的方式來得到41種區塊的移動向量。
最後使用verilog硬體描述語言來實現其電路架構，再透過Synopsys的Design Compiler與TSMC 0.18㎛製程作電路合成，實驗結果顯示，本論文所提出的三步搜尋法移動估測架構，比起以往的三步搜尋法可得到更多區塊大小的移動向量，比起以往的可變區塊大小硬體架構雖然面積並沒有減少，但確實降低了運算複雜度。

H.264/AVC plays an important role in the video compression standard, it is better than previous video standards in the compression ration and the image quality. Motion estimation is one of the core designs of H.264 video coding, it basically includes the motion vector at quarter pixel resolution with variable block sizes and multiple reference frames, it is mainly to improve the image quality and provides more accurate predictions, however, because of these features, the computation load and complexity of motion estimation increase significantly.
This thesis proposes VLSI architecture for variable block size motion estimation which applies to the three step search algorithm. Our proposed architecture use pipelined design and employs parallel architecture to improve the throughput, in the processing elements, it allows SADs for larger block sizes to be computed by using the results derived for 4x4 blocks.
Finally, we implement the RTL code by Verilog hardware description Language, and synthesize the digital circuit by using Design Compiler of Synopsys with the TSMC 0.18㎛CMOS technology. Experimental results show that, Compared with the conventional three step search architectures, our proposed architecture can obtain more motion vectors for different block size, and compared to the previous variable block size architectures, our proposed architecture can reduce the computational complexity.

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