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研究生： 陳雅琪
Chen, Ya-Chi
論文名稱： 採用數位預先校準技術之0.7伏特10位元低功率循環式類比數位轉換器
A 0.7-V 10-bit Ultra-low Power Cyclic A/D Converter with Digital Foreground Calibration
指導教授： 劉濱達
Liu, Bin-Da
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2006
畢業學年度： 94
語文別： 英文
論文頁數： 59
中文關鍵詞： 低電壓 、數位預先校準 、類比數位轉換器 、低功率
外文關鍵詞： low power, digital foreground calibration, analog-to-digital converter, low voltage
相關次數： 點閱：113  下載：5 
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    • 隨著製程技術的演進，各種大型的生物醫學器材也逐漸的縮小化，甚至更進一步地整合成植入式生醫晶片，針對這方面的應用需求，具有低電壓和低功率消耗能力的積體電路已經成為積體電路設計上的主流與挑戰。
    本論文中，我們實現一個應用於植入式生醫感測器的低電壓、低功率消耗的類比數位轉換器，採用可以提供具有可靠性解決方案的切換式運算放大器技術，使得電路不需要特殊製程和增加時脈訊號電壓的電路，能夠在低供應電壓的條件下正常地操作。此外，我們設計運算放大器及比較器的所有MOS元件都操作在弱反轉區，大大地降低了電路的功率消耗，更使用數位預先校準技術，校準類比數位轉換器的輸出，提高輸出結果的精確度。
    我們使用台積電0.13微米一層多晶矽八層金屬之互補式金氧半導體製程，實現一個供應電壓為0.7伏特、輸出10位元的數位訊號、取樣頻率為1千赫茲、低功率消耗且能自我校準的循環式類比數位轉換器。在使用校準電路的情形下，即使採用一低增益(53 dB)但線性的運算放大器，仍可得到一訊號對於雜訊及諧波失真比高達58.86 dB 的循環式類比數位轉換器。整個電路不包含數位校準的功率消耗為2 μW。

    This paper describes a low supply voltage and ultra-low power integrated analog-to-digital converter (ADC) for implantable bio-medical sensor applications. Through biasing the opamps and comparators in the weak-inversion region and adopting switched-opamp technique into the ADC architecture allows for the circuit operation with low supply voltage and ultra-low power consumption. A 0.7-V 10-bit 1 ksample/s ultra-low power cyclic analog-to-digital converter (ADC) is proposed, which is itself calibrated in the foreground and implemented with 0.13μm TSMC 1P8M CMOS technology. The calibration overcomes the circuit non-idealities caused by capacitor mismatch and finite operational amplifier (opamp) gain in the cyclic ADC. With the digital foreground calibration, the peak signal-to-noise ratio is 58.86 dB with a low gain (53 dB) but linear opamp. The total power dissipation is 2 μW not including the calibration circuit.

    Chapter 1 Introduction 1 1.1 Motivation and Goal 1 1.2 Thesis Organization 3 Chapter 2 Behavioral Model and Design Techniques of Low-Voltage Cyclic Analog-to-Digital Converter 4 2.1 Behavioral Model of Cyclic ADC with Non-idealities 5 2.1.1 The Behavioral Models of Key Building Blocks of Cyclic ADC 5 2.1.2 Non-idealities in Cyclic ADCs 10 2.1.3 Complete Behavioral Model of Cyclic ADC 21 2.2 Low-Voltage Switched-Capacitor Techniques 22 2.2.1 Voltage Multiplier 24 2.2.2 Bootstrapped Switch 26 2.2.3 Low-Threshold Voltage Process 27 2.2.4 Switched Opamp Technique 28 2.3 Summary 29 Chapter 3 The Implementation of Proposed Low-Voltage Cyclic ADC 30 3.1 Low-Voltage Sample-and-Hold Circuit 31 3.1.1 Implementation of Bootstrapped Switch 32 3.1.2 Simulation Results of Sample-and-Hold Circuit 33 3.2 Low-Voltage Multiplying Digital-to-Analog Converter 35 3.2.1 Conventional MDAC of 1.5-Bit/Stage ADC Architecture 35 3.2.2 Low-Voltage MDAC 36 3.3 Low-Voltage Ultra-Low Power Switched Opamp 38 3.4 Summary 41 Chapter 4 Foreground Calibration and Simulation Results 42 4.1 Calibration of Cyclic ADC 43 4.1.1 Digital-Calibration Algorithm 43 4.1.2 The Behavioral Model of Calibration Circuit 49 4.2 The Simulation Results of Low-Power Cyclic ADC 50 4.3 Summary 54 Chapter 5 Conclusions and Future Work 55 5.1 Conclusions 55 5.2 Future Work 56 References 57

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