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研究生： 吳旻鴻
Wu, Ming-Hung
論文名稱： 具有功率效益和預防因製程、電壓、溫度變異所造成電路錯誤的嵌入式脈衝時序預測器設計
A Power-efficient Pulse-based In-situ Timing Error Predictor for PVT-sensitive Circuits
指導教授： 邱瀝毅
Chiou, Lih-Yih
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2011
畢業學年度： 99
語文別： 英文
論文頁數： 78
中文關鍵詞： 動態電壓調整 、嵌入式時序錯誤預測器 、製程、電壓、溫度變異
外文關鍵詞： Dynamic voltage scaling, In-situ timing error predictor, PVT variations
相關次數： 點閱：133  下載：1 
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    • 隨著先進製程的微縮，使得製程、電壓、溫度的變異明顯的增加，而這些有可能導致運行中的微處理器發生時序錯誤。在傳統的設計中，積體電路設計者考慮所有最壞的情況並加入大量的安全區域去容忍製程、電壓、溫度變異的影響，但是系統設計考量在悲觀的假設下，將同時帶來不合預期的功率消耗及額外面積佔據。因此，可調節式的設計已成為電路設計者的關注，因為可調節的設計可同時舒緩變異的影響及減輕上述的負擔。在本篇論文當中，則提出了可適用於動態電壓調整機制系統的嵌入式脈衝時序預測器的兩種架構設計：第一種的設計是採用主要拴鎖器的資料轉態來產生脈衝，並利用脈衝來預測時間錯誤；第二種的設計是採用雙取樣的設計來預測及偵測時間錯誤。這二種的設計均應用在即時系統中來當作驗證，並使用TSMC 0.18µm CMOS製程去製造。經由下線晶片的量測結果中指出，所提出的兩種架構裝載在乘加器的單元上皆可正常運行。

    With the advancement of technology scaling, PVT variations are increasingly significant that could cause the timing errors during operation of microprocessors. Traditionally, IC designers consider the worst case condition and use a large safety margin to increase the tolerance of process, voltage and temperature (PVT) variations. The system designed under pessimistic assumption may consume unnecessary power consumption and occupy extra area simultaneously. Consequently, the IC’s designer is interested in adaptive design approaches to mitigate the PVT variation and reduce those overheads simultaneously. In this thesis, we proposed two in-situ timing error monitors, which could support the dynamic voltage scaling system. The first monitor is to generate a pulse during data transition along with a master latch to predict the timing error. The other one enhances the double sampling scheme to predict and detect timing errors. The two designs are then verified and fabricated using TSMC -0.18µm on realistic systems. The measurement results of the fabricated chips indicate that multiplier-and accumulator (MAC) units equipped with two proposed monitors work successfully.

    Abstract (Chinese) i Abstract (English) ii Achnowledgement (Chinese) iii Contents iv List of Tables vii List of Figures viii Chapter 1 Introduction 1 1.1 Preliminary 1 1.1.1 Process Variation 2 1.1.2 Voltage Variation 3 1.1.3 Temperature Variation 4 1.2 Motivation 6 1.3 Contributions 7 1.4 Thesis Organization 8 Chapter 2 Adaptive Approaches 9 2.1 Adaptive Design Approach 9 2.2 Open-loop and Closed-loop Techniques 10 2.3 Error Detection and Correction Circuit Design 14 2.3.1 Razor I flip-flop and recovery architecture 14 2.3.2 Razor II flip-flop and recovery architecture 18 2.4 Error Prediction Circuit Design 21 2.4.1 Replica-path 21 2.4.2 In-situ Triple latch monitor 22 2.4.3 In-situ Sensor flip-flop 23 2.4.4 In-situ Canary flip-flop 25 2.5 Summary 27 Chapter 3 Proposed Pulse-based Circuit Design 30 3.1 Transition Pulse Canary Flip-Flop (TPC) 30 3.2 Gating Clock Canary Flip-Flop (GCC) 33 3.3 Transistor-level Design of the Proposed TPC and GCC Flip-flops 36 Chapter 4 Simulation Results 39 4.1 Pre-layout Simulation Environment Setup 39 4.1.1 Pre-layout simulation for proposed TPC design 41 4.1.2 Pre-layout simulation for proposed GCC design 45 4.1.3 Compare with experiments circuit 46 4.2 Giga Hertz Simulation for Proposed Designs 49 4.3 Architecture of Multiplication-and-accumulator Unit 51 4.4 PVT simulations for proposed designs 52 4.5 Chip Block Diagram 55 4.6 Post-layout Simulation for MAC 58 4.7 Compare with Conventional Canary MAC 64 4.7.1 Compare with power consumption 64 4.7.2 Area 65 4.8 Layout and Chip Implementation 66 4.8.1 Layout for transition pulse canary 67 4.8.2 Layout for gating clock canary 68 4.9 Test chips and Measurement Results 69 Chapter 5 Conclusions and Future Works 73 5.1 Conclusions 73 5.2 Future Works 74 Reference 75

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