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研究生： 郭子齊
Kuo, Tzu-Chi
論文名稱： 用於系統階層以資料導向追蹤記錄方式探索通訊架構的功率及效能之研究
Power and Performance Exploration for System-Level Communication Architecture Using Trace-Driven Approach
指導教授： 邱瀝毅
Chiou, Lih-Yih
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2007
畢業學年度： 95
語文別： 英文
論文頁數： 91
中文關鍵詞： 探索通訊架構 、功率 、系統階層 、資料導向追蹤 、效能
外文關鍵詞： communication architecture exploration, performance, system-level, power, trace-driven
相關次數： 點閱：117  下載：1 
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    • 在現今快速成長的系統單晶片中，其系統單晶片的日漸複雜程度讓現今系統設計者已無法只使用傳統的設計方式，來造成無法順利達到產品設計、製造至投入市場的所需時間。對於系統設計者來說，無疑是個巨大的設計挑戰。因此在本篇論文當中，我們提出一個於系統階層中去探索以及分析系統通訊架構的方法，以協助系統設計者能夠在初期的設計架構中，探索出初步最佳功率以及效能的通訊架構系統。同時在探索通訊架構中我們提出一個演算法，能夠避免重複探索不必要的系統設計。另外在本篇論文中，我們所提的探索方法是運用了資料導向的追蹤方式，去記錄系統的內部功能傳輸資料，且針對此追蹤出來的資料進行初步的非功能性分析。之後導入通訊架構探索演算法，來得到初步較佳功率以及效能的系統通訊架構，且導入系統通訊架構中的參數去分析其效能以及功率的損耗。所評估出來的通訊架構以及效能與功率消耗，將可協助系統設計者去探索可能的初期系統通訊架構，以便於之後的系統設計。另外在探索的結果中，可以清楚地快速探索出初期最佳功率與效能的通訊架構，而不用經過探索分析所有可能的通訊架構。另外可以在系統階層的角度中，就可以觀察到其不同的通訊架構會顯著地影響整體系統的功率與效能，再加上快速探索及分析的速度可以協助設計者快速設計出市場所需的系統。

    The system-on-chip (SoC) grows rapidly in modern era, system designers could not only use traditional system design methods to design SoC. Traditional system design methodologies are difficult to meet time-to-market and customer’s requirements. Therefore, we proposed a novel methodology and exploring architecture algorithm to optimize communication architecture for both power and performance. The methodology could assist system designers to reduce some of possible communication architecture exploration, in other words, we do not have to explore all possible communication architectures. Hence designers could obtain the initial communication architecture system with optimizing power under performance constraint and performance under power constraint. In addition, system designers could observe the influence of total system power and performance with different communication architectures at system level. Furthermore, fast analysis and communication architecture exploration will give designer referenced power/performance information to accelerate the system design process.

    Chapter 1 Introduction 1 1.1 Breakdown of Power Consumption 1 1.2 Impacts of Early Design Exploration 3 1.3 Accuracy and Simulation Speed 5 1.4 Thesis Contributions 6 1.5 Thesis Organization 6 Chapter 2 Power and Performance Estimation for System-Level Communication Architectures 8 2.1 System-Level On-Chip Communication Architecture Power Estimation 8 2.1.1 Fast System-Level Power Profiling 9 2.1.2 Power Estimation of Parameterized Cache and Bus Architecture 10 2.2 System-Level On-Chip Communication Architecture Performance Estimation 12 2.3 Trace-Driven System-Level Power Estimation of Communication Architecture 14 Chapter 3 Power and Performance Optimization for System-Level Communication Architectures 17 3.1 System-Level On-Chip Communication Power Optimization 17 3.1.1 Split Communication Architecture 18 3.1.2 Bus Encoding Technique 20 3.2 System-Level On-Chip Communication Performance Optimization 21 3.2.1 Design Space Exploration for Optimizing 22 3.2.2 SLCAO Methodology 24 3.2.3 Efficient exploration of bus-based system-on-chip architecture 25 Chapter 4 Proposed Power and Performance Exploration for System-Level Communication Architecture Using the Trace-Driven Approach 28 4.1 Overview 29 4.2 Trace Construction and Analysis 31 4.2.1 Trace Construction 32 4.2.2 Trace File Analysis 34 4.3 Communication Architecture Mapping 35 4.3.1 Insertion of Communication Tasks 35 4.3.2 Bus Arbitration and Priority 38 4.4 Power/Performance Analysis 39 4.4.1 Power and Performance Analysis 39 4.4.2 Proposed Analysis versus CoWare ConvergenSC 42 4.4.3 Memory Analysis 48 4.5 Architecture Exploring Algorithm 51 4.5.1 Flow Chart of the Proposed Architecture Exploring Algorithm Flow 51 4.5.2 A Brief Example of Architecture Exploring Algorithm 54 4.6 Summary of the Proposed Methodology 56 Chapter 5 Case Study: a H.264 Decoder System 58 5.1 Preliminary 58 5.2 Experiment Result and Discussion 62 5.2.1 Setting H.264 Decoder in the Novel Methodology 63 5.2.2 Bus Burst and Bandwidth vs. Bus Execution Cycles 66 5.2.3 Bus Burst and Bandwidth vs. Global Memory 71 5.2.4 Bus Bandwidth vs. Bus Energy 73 5.2.5 Bus Utilization 75 5.2.6 Different Number of Shared Buses 79 Chapter 6 Conclusions and Future Works 85 6.1 Conclusions 85 6.2 Future works 86 References 87

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