在本論文中，我們針對60 GHz毫米波前端電路之主要元件(包括低雜訊放大器及混頻器)進行設計。所有電路均使用TSMC CMOS 0.13 μm或TSMC CMOS 90 nm製程進行製作。在不使用SiGe或III-V等昂貴半導體製程的狀況下，TSMC提供的先進CMOS製程可使得電路在60 GHz的高頻率下仍有優秀的效能表現。
本論文分成三大部分。第一部份為使用CMOS 0.13 μm製程設計一個應用於V-band之低雜訊放大器。本電路使用三級串接之疊接放大器架構，供應電壓為1.2 V。使用on-wafer量測結果顯示，消耗功率為25.2 mW；在54-61 GHz的範圍內增益仍皆在10 dB以上，最大增益值出現在57 GHz為14.6 dB；最佳雜訊指數出現在58.5 GHz為6.9 dB；與預期60 GHz之操作頻率相比增益及雜訊指數的頻率漂移小於3 GHz。
第二部分為使用CMOS 90 nm製程設計一個應用於60 GHz WPAN與UWB共存系統之降頻混頻器，使用的架構為雙平衡式吉伯特混頻器。為求能獲得寬中頻之響應頻寬，本混頻器之負載級使用了可變電容與標準螺旋電感構成共振腔作為電路之負載。同時在構成匹配網路的傳輸線部分使用了slow-wave效應以縮短傳輸線長度。本電路採用on-wafer的量測結果顯示，中頻之3-dB頻寬可達2.1 GHz；同時，在供應電壓為1.2 V的情況下消耗功率僅為13.9 mW(包含緩衝器)。在線性度方面，輸入頻率為58.5 GHz時量測所得之IIP3為+0.6 dBm。最佳雜訊指數出現在輸入頻率為57.2 GHz時大小為15.95 dB。在LO-RF、LO-IF及RF-IF三種隔離度方面均大於25 dB。
最後，第三部分為使用CMOS 90 nm製程整合升頻混頻器及發射放大器之電路。此電路可將5 GHz之IF訊號升頻至60 GHz，並整合一級可放大訊號的發射放大器用來推動後級之功率放大器。在升頻混頻器部分同樣採用雙平衡式吉伯特混頻器架構，升頻至60 GHz之差動訊號藉由螺旋狀馬遜平衡不平衡轉換器轉成單端訊號，再透過兩級之發射放大器放大至0 dBm。模擬結果顯示，本電路在RF頻率59-63 GHz內提供了10 dB以上的增益；在60 GHz該頻率下輸出1 dB壓縮點為+0.8 dBm，而飽和輸出功率為5.7 dBm。
綜合上面三部分所述，我們證實使用TSMC之先進CMOS製程確實可實現60 GHz射頻前端電路之設計。同時，本論文完成了60 GHz毫米波前端電路之低雜訊放大器及混頻器設計及量測，這些成果將有助於完整前端收發機電路之實現。

In this thesis the main components of 60 GHz millimeter-wave front-end, including a low-noise amplifier and two mixers, have been designed. All the circuits were implemented in TSMC CMOS 0.13 μm or TSMC CMOS 90 nm process. Without using high-cost SiGe or III-V compound semiconductor processes, the advanced CMOS processes provided by TSMC make these circuits achieve high performance in the frequency regime as high as 60 GHz.
This thesis is mainly divided into three parts. In the first part of the thesis, a low-noise amplifier applied for V-band has been designed by using a CMOS 0.13 μm process. The circuit adopted a structure involving three stages of cascode amplifiers. The on-wafer measurement results show that the power consumption is 25.2 mW under supply voltage of 1.2 V, the gain is better than 10 dB in the frequency range of 54-61 GHz, the maximum gain of 14.6 dB appears at 57 GHz, and the minimum noise figure of 6.9 dB locates at 58.5 GHz. The power gain peak and minimum noise figure data exhibit the frequency shift less than 3 GHz as compared with the expected center frequency of 60 GHz.
The second part of the thesis demonstrates a down-conversion mixer design for a 60 GHz WPAN and UWB coexistence system by using a 90 nm process. Based on the double-balanced Gilbert-cell structure, the LC tank which is composed of spiral inductor and MOS varactors is used as the load stage to achieve a wider IF bandwidth. Slow-wave transmission lines are also integrated to reduce the line length for the impedance matching network. The down-conversion mixer exhibits that the 3-dB bandwidth of the IF port reaches 2.1 GHz wide. The circuit draws only 13.9 mW (including the buffer stage) at a supply voltage of 1.2 V. The measured IIP3 is +0.6 dBm at RF input frequency of 58.5 GHz. The minimum NF is 15.95 dB at 57.2 GHz. Three kinds of port-to-port isolations include LO-RF, LO-IF and RF-IF, are all better than 25 dB.
The last part of this thesis focuses on the integration for an up-conversion mixer and a transmitting amplifier. The IF signal will be converted from 5 GHz up to 60 GHz and be amplified through the transmitting amplifier to drive the following power amplifier stage. The differential signal at double-balanced Gilbert-cell output will be transformed to a single-phase signal through a Marchand balun and be amplified to 0 dBm. The simulation result shows power gain are better than 10 dB in the 59-63 frequency range. The OP1dB is +0.8 dBm and saturated output power is 5.7 dBm under 60 GHz.
According to the above-mentioned designs, it's feasible to implement 60 GHz front-end by using advanced CMOS process. At the same time, we have implemented a low-noise amplifier and a mixer for 60 GHz millimeter-wave designs, which are helpful to the complete 60 GHz front-end transceiver integration in the future. .

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