隨著製程特徵尺寸的縮小，整合大型並且複雜的設計至一單晶片已經成為IC設計領域中主要的趨勢。然而，單晶片系統的設計方法同時也帶來了許多問題。除了電路與系統設計的問題外，最為嚴重的問題就是如何針對單晶片系統進行測試與除錯。因此，在本論文中，提出一涵蓋硬體與軟體設計的單晶片系統除錯平台。
　　本論文所提出之單晶片系統除錯平台支援針對核心電路的除錯技術，包括設置硬體中斷點與單步執行。當核心電路在執行正常運算時，我們提供使用者暫停與恢復的功能，藉以獲得電路中詳細的內部資訊。而此除錯平台具有下述的優點，透過重覆使用測試元件以達到低面積負擔，以及提供許多種除錯的模式來提高使用彈性。此外，我們也發展一套使用者圖形介面來與除錯平台共同運作。經由此設計自動化工具，使用者將可以更容易的控制除錯動作，並且更有效率的接收與比對除錯結果，以判別矽晶片中錯誤的根源。實驗結果顯示，所提出之除錯平台是一實際可行的方法，用以解決矽晶片除錯問題。

With the scaling down of feature sizes, integrating large and complex design into a single chip is becoming the main trend in IC design. However, such system-on-a-chip (SoC) design methodology introduces many problems as well. Besides circuit/system design, the most critical problem is testing and debugging of SoC systems. In this thesis, we present a　SoC debug platform to address this problem.
The developed debug platform supports multi-core debug technology inclusive of cycle-based breakpoint insertion and single step for general purpose cores/IP on a SoC chip. We allow users to suspend and restore the normal operation to obtain detailed information in the CUDs (Cores Under Debug). This platform has the advantages of low area overhead by reusing test components and high flexibility by providing several debug modes. Also, we develop a graphic user interface to support this on-chip debug platform. With this design automation tool, users can easily control the debug operation and receive traced results to identify the root-cause of failures in the silicon easily and efficiently. Experimental results show that the proposed debug platform is a practical solution for silicon debug problem.

References
[1] Bart Vermeulen, “Functional Debug Techniques for Embedded Systems”, IEEE Design & Test of Computers, pages 208-215, 2008

[2] Liang-Bi Chen, Yung-Chih Liu, Chien-Hung Chen, Chung-Fu Kao, and Ing-Jer Huang, “Parameterized Embedded In-circuit Emulator and Its Retargetable Debugging Software for Microprocessor/Microcontroller/DSP Processor”, IEEE ASPDAC, pages 117-118, 2008

[3] Yi-Ting Lin, Wen-Chi Shiue, and Ing-Jer Huang, “A Multi-resolution AHB Bus Tracer for Real-time Compression of Forward/Backward Traces in a Circular Buffer”, DAC, pages 862-865, 2008

[4] Shan Tang and Qiang Xu, “A Debug Probe for Concurrently Debugging Multiple Embedded Cores and Inter-Core Transactions in NoC-Based Systems”, IEEE ASPDAC, pages 416-421, 2008

[5] Chung-Fu Kao, Ing-Jer Huang, and Chi-Hung Lin, “An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration”, DAC, pages 477-482, 2007

[6] Jian-Jhih You and Kuen-Jong Lee, “High-Performance Component Design for SoC Test Platforms with Mixed-Signal Test Capability”, Master Thesis, Dept. of E.E., NCKU, Taiwan, 2007

[7] Shan Tang and Qiang Xu, “A Multi-Core Debug Platform for NoC-Based Systems”, DATE, pages 1-6, 2007

[8] Wen-Cheng Huang, Chin-Yao Chang and Kuen-Jong Lee, “Toward Automatic Synthesis of SoC Test Platform”, VLSI Design, Automation, and Test, pages 1-4, 2007

[9] Yu-Chin Hsu, Furshing Tsai, Wells Jong, and Ying-Tsai Chang, “Visiblity Enhancement for Silicon Debug”, DAC, July, pages 13-18, 2006

[10] Kuen-Jong Lee, Chia-Yi Chu, and Yu-Ting Hong, “An Embedded Processor Based SoC Test Platform”, Proc. Int’l Symp. on Circuits and Systems, pages 2983-2986, 2005

[11] Ming-Long Wu and Kuen-Jong Lee, “Performance Analysis and Enhancement of SoC Test Platform”, Master Thesis, Dept. of E.E., NCKU, Taiwan, 2005

[12] P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, “Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores”, IEEE Microprocessor Test and Verification, pages 55-62, 2005

[13] Wilco de Boer, Bart Vermeulen, “Silicon Debug: Avoid Needless Respins”, IEEE/SEMI Int’l Electronics Manufacturing Technology Symposium, pages 277-281, 2004

[14] Bart Vermeulen, S. Kumar Goel, “Design for Debug: Caching Design Errors in Digital Chips”, IEEE Design & Test of Computers, pages 35-43, 2002

[15] Ing-Jer Huang, Chung-Fu Kao, Hsin-Ming Chen, Ching-Nan Juan, and Tai-An Lu, “A Retargetable Embedded In-Circuit Emulation Module for Microprocessors”, IEEE Design & Test of Computers, pages 28-38, 2002

[16] Yu-Ting Hong and Kuen-Jong Lee, “An Embedded-Processor-Driven Platform for SoC Testing”, Master Thesis, Dept. of E.E., NCKU, Taiwan, 2002

[17] ARM Ltd. Web Site, http://www.arm.com

[18] AMBA Specification, http://www.arm.com

[19] ChipScope Pro Software and Cores User Guide, Xilinx Inc.

[20] IEEE 1500 Standard for Embedded Core Test (SECT), http://grouper.ieee.org/groups/1500/

[21] IEEE Computer Society, “IEEE Std. 1149.1: IEEE Standard Test Access Port and Boundary-Scan Architecture”

[22] “The Source For Perl”, http://www.perl.com/

[23] VERSATILE PLATFORM BASEBOARD User Guide, http://www.arm.com

[24] VERSATILE/LT-XC2V4000+ User Guide, http://www.arm.com