針對矽晶片除錯技術中，運作中停下並恢復除錯方法能藉由將電路停下時脈，並透過測試架構中的掃描練擷取電路內部暫存器之狀態，當使用者設定下一個時脈中斷點來得到更多的除錯資訊時，電路時脈將被恢復繼續運作，直到下一個中斷時脈到達。此除錯方法亦被應用在能以系統匯流排協定進行資料交換的系統單晶片。然而在先前相關方法文獻的探討主要以完成整個資料交換動作或訊號交換完成一次為除錯解析度，舉例來說，當停下之時脈成立於資料正在進行中，此除錯解析度必須等到整個資料完成後或其中一筆訊號交換完成才能被停下。若使用此除錯解析度，使用者將會損失許多電路內部資訊。因此在本篇論文中，我們提出一個能在任一時脈週期停下並恢復電路之硬體除錯技術，並稱之為停下並恢復代理機制。此代理機制能讓停下並恢復除錯方法以時脈周期解析度停下，使得使用者能任意觀察到電路內部資訊。停下並恢復代理機制能處理因電路時脈被中斷時，使得未完成的資料交換或訊號動作違反系統匯流排之規定與資料交換錯誤等問題，來大大地增加系除錯流程的彈性與效率。在實驗結果中，實現停下並恢復代理機制所需付出的面積與效能代價非常低，在SoC設計中甚至可以忽略不計;除此之外，時脈週期的除錯解析度能讓使用者可在硬體中斷點發生時立即觀察電路內狀態，相較於之前文獻的除錯解析度，可從電路中擷取的除錯資訊之比率能達到百分之百，進而大幅增進矽除錯效率。

The run-pause-resume silicon debug approach allows users to pause the normal (system) operations of the circuits under debug (CUDs), extract the internal states of the CUDs for examination, and then resume the normal operations for further debugging. However, most previous work on this approach cannot pause the CUD until a transaction or handshake completes. The user is going to lose many internal information of the CUD because the transaction or a handshake operation requires a large number of cycles to complete. In this paper, we present a novel debug mechanism, called the Pause-Resume Agency Mechanism (PRAM), which allows the user to pause the CUD at the arbitrary cycle and resume the CUD to get more information, even if the transaction or handshake is processing. The PRAM can deal with transaction invalidation as well as protocol violation that may occur when a system is paused and resumed. Experimental results on several industry circuits show that the area overhead of the PRAM is quite small and the performance impact on the system is negligible. The ratio of interruptible clock cycles achieves 100%.

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