隨著半導體製程之演進，愈來愈多核心電路被整合進系統單晶片(System-on-a-chip)，以軟體為基礎的模擬方式己經無法保證實際的晶片能正常運作。所以使用者常常浪費大量時間去除錯或驗證系統單晶片，為了有效節省除錯及驗證時間，使用者需要一套有系統的除錯方法。
在此篇論文裡，我們發展出一套具有除錯機制的系統單晶片除錯平台。此除錯平台包含了硬體及軟體設計，它支援在核心電路執行正常運算時，同時擷取系統匯流排或核心電路的輸入/輸出埠的資訊。另外，為了有效減少擷取的資料量，我們也發展了資料壓縮及分段擷取的技術來解決此問題。由於現今愈來愈多系統單晶片都整合了測試元件，所以我們重覆利用測試元件支援除錯的機制達到降低成本目的。此除錯平台也提供一個具有軟/硬體一起驗證的(co-verification)機制，此機制可以自動地比對擷取結果與預期結果是否有錯誤產生，可有效節省驗證時間。
最後，為了讓我們所發展除錯機制更人性化，一個以圖形介面為基礎的除錯軟體也被提出，使用者可利用此軟體快速將核心電路整合進我們所提出的系統單晶片除錯平台，此除錯軟體也提供互動式的介面讓使用者設定除錯參數並顯示除錯結果。

As the increasing complexity of IP cores integrated into a SoC, software-based simulation model cannot ensure that first silicon will work correctly. Debugging and verification for first silicon are often time-consuming. Therefore, designers need an efficient approach to catch design errors while debugging. In this thesis we propose debug platform contains hardware/software designs. Within the proposed debug platform, we develop a novel real-time system monitor, called the on-line trace. When intellectual property (IP) cores are under normal operation, the on-line trace mechanism can monitor and capture data simultaneously. To reduce trace data volume, we also develop a data compression with time division technique to reduce trace data size. Furthermore, we reuse original test components to reduce area overhead. A friendly graphic user interface is also provided to bring conveniences to designers for rapidly building a debug platform and analyzing trace data from the real chip.

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