本論文針對近似ANSI S1.11 Class-2規格，提出設計18個頻帶濾波器組的演算法及硬體實現架構。濾波器組設計流程主要分為幾部分：(1)使用1組低通濾波器搭配9次離散餘弦調變，產生9個頻帶的等頻寬濾波器組；(2)將FIR架構中的延遲單元替換成全通濾波器，使等頻寬濾波器組變成非等頻寬濾波器組，調整參數使其符合規格的頻帶31至39；(3)套用多速率架構，使用頻帶31至39濾波器組架構，只透過調整輸入訊號取樣頻率來濾出頻帶22至30；(4)針對係數重複性將輸入摺疊，並改良M值選擇，進一步降低運算量。
在硬體設計方面，將每個區塊分別做位元數分析，減低硬體成本，並且將各區塊運算管線化，大幅降低即時化時脈速率。硬體電路實現於FPGA開發版，並使用板子上的CPU進行軟硬體整合驗證。
與近年的Liu et al.文獻做比較，本論文每個取樣點的乘法降低59%，加法降低16%，係數量更大幅降低78%，匹配誤差以及電路即時化速率也落在差不多量級。整體而言，本論文提出之濾波器組具備低群延遲、低運算量及低即時化時脈速率，與助聽器的設計取向契合，適合應用於助聽輔具中。

This thesis presents an algorithm design and hardware implementation for 18-band quasi-class-2 ANSI S1.111/3 octave filterbank, which achieves low computational complexity and group delay. The develoging technique of this thesis is summarized as follows: 1) integrate a prototype low-pass filter and discrete cosine transform modulation to realize a 9-band uniform filterbank; 2)replace all z-1 elements of FIR by all-pass filters to abtain an non-uniform filterbank, which meet the band 31-39 of ANSI spec; 3)apply multi-rate structure to filter band 22-30, which use the same filterbank structure with band 31-39 but alternate the sampling rate of input signal; 4)reduce the computational complexity by coefficient repeatability and improvement of DCT length “M” selection. The proposed analysis filter bank was implemented at FPGA, the wordlength of each block was analyzed separately to lower the hardware cost, and applied pipelined scheduling to reduce operating cycle. Integrate the CPU of FPGA with our circuit to verify the accuracy. Compare with the researchs of recent years, this thesis present a good performance of group delay, computation complexity and real-time clock rate, which is suitable for the application of digital hearing aids.

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