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研究生： 吳政鴻
Wu, Cheng-Hung
論文名稱： 適用於多種錯誤模型之邏輯電路測試與診斷方法
Test and Diagnosis Methodology for Various Fault Models in Logic Circuits
指導教授： 李昆忠
Lee, Kuen-Jong
學位類別： 博士
Doctor
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2018
畢業學年度： 106
語文別： 英文
論文頁數： 124
中文關鍵詞： 測試向量產生方法 、錯誤診斷 、診斷向量產生方法 、多錯誤模型 、診斷修復架構
外文關鍵詞： Test pattern generation, fault diagnosis, diagnosis pattern generation, various fault models, repair-for-diagnosis architecture
相關次數： 點閱：126  下載：5 
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    • 近年來隨著先進製程技術的快速演進，單一電晶體面積已大幅下降，線距亦急劇減小，產生出許多未建立模型之缺陷，無法使用目前常用的錯誤模型解釋，因此業界需使用多種常見錯誤模型的測試向量來提升缺陷覆蓋率(Defect Coverage)，使整體測試流程花費相當長的時間。然而過低的缺陷覆蓋率也導致後段錯誤診斷無法有效診斷出真實缺陷的位置與型態。
    在這篇論文中，我們提出適用於多種錯誤模型的測試與診斷向量產生技術，以解決因測試資料量與診斷資料量過於龐大造成測試與診斷成本過高的問題。我們分別應用此技術到各種錯誤模型，包含常見的時間相關錯誤模型(Time-Dependent Fault Model)、時間無相關模型(Time-Independent Fault Model)與未建立模型之缺陷，藉由一般業界常用的自動測試向量產生工具(Commercial ATPG Tool)，產生出具有高壓縮率的測試與診斷向量，能同時測試多種錯誤模型來提升缺陷覆蓋率以及有效分辨電路缺陷的位置與型態，不僅加速晶片的測試流程，也能提高後段錯誤診斷的效率，達到大幅降低測試與診斷時間成本。
    其中，經由我們的技術產生的診斷向量能有效率地分辨出電路中的缺陷位置與型態，然而，由於電路本身的限制，存在許多無法藉由診斷向量分辨的缺陷(Test-Equivalent Faults)，在我們的論文中，我們進一步提出一診斷修復技術來分辨這些缺陷，藉由置入多餘的邏輯閘與電晶體來修復缺陷，判斷缺陷是否能被成功修復，達到分辨出電路真實缺陷的位置。我們可應用此技術到尚未成熟的新製程中，藉由修復測試電路(Test Chip)來快速找出真實缺陷位置，能有效提升新製程的良率。

    With the shrinking manufacturing process and increasing design complexity, the defect behaviors in contemporary integrated circuits have become much more complex than ever. It is generally realized that the test set for a simple, single fault model such as the stuck-at fault model or transition delay fault model is insufficient to detect all defects. Hence, it is necessary to use more accurate, and often more than one fault model in order to avoid test escapes and increase defect coverage, resulting in long test time for whole test and diagnosis flow. The low defect coverage also causes that the diagnosis analysis tool cannot identify the fault site and location of real defect efficiently.
    In this dissertation, we propose the test and diagnosis methodology to deal with various fault models to reduce the cost problems due to large amount of test and diagnosis data volume. We apply our methodology to various fault models, including time-dependent fault models, time-independent fault models and undefined defects. By using a commercial ATPG tool, a compact set of test and diagnosis pattern can be generated to detect various fault models and distinguish the fault pair that consists of two faults. Not only speeding up the whole test and diagnosis flow but also increasing the efficiency of diagnosis analysis (identify the defect location and defect type), resulting in much lower test and diagnosis cost.
    The generated diagnosis patterns can help us identify the real defect efficiently. However, due to the limitation of logic circuit, there are still many functionally-equivalent faults that cannot be distinguished by any possible test. In our dissertation, we develop a repair-for-diagnosis architecture to help us distinguish those functionally-equivalent faults. Bu adding the redundant transistors or redundant gates into the fault site of those functionally-equivalent faults, we can identify the location and type of real defect if repairing is successful. We can apply this repair-for-diagnosis architecture to new advance manufacturing process to identify the real defect quickly and improve chip yields efficiently.

    CHAPTER 1 Introduction 1 1.1 Motivation 1 1.2 Overview 2 1.3 Organization 6 CHAPTER 2 Previous Work 8 2.1 Test Methodology 8 2.2 Diagnosis Methodology 10 2.3 Repair-for-Diagnosis 12 CHAPTER 3 Test Pattern Generation Procedure for Various Fault Models 14 3.1 Exiting Fault Models & Undefined Fault Model 15 3.1.1 DC-Scan Fault Models 15 3.1.2 AC-Scan Fault Models 17 3.1.3 Undefined Fault Models 18 3.2 Unified Fault Model 19 3.2.1 Static Bridging Fault (SBF) 19 3.2.2 Dynamic Bridging Faults (DBFs) 19 3.2.3 Circuit Modification for Fault Transformation 20 3.3 Test Generation for DC-Scan Fault Models 22 3.3.1 Fault-based Transformation Method for Cell-External Faults 22 3.3.2 Pattern-based Transformation Method for Cell-Internal Faults 26 3.3.3 Test Pattern Generation Procedure 29 3.4 Test Generation for AC-Scan Fault Models 31 3.4.1 Fault-based Transformation Method for Transition Delay Faults 31 3.4.2 Fault-based Transformation Method for Open and Delay Faults inside CMOS Cell 32 3.4.3 Path-based Transformation Method 34 3.4.4 Test Pattern Generation Procedure 36 3.5 Results and Comparisons 37 3.5.1 Results for Cell-External Faults 37 3.5.2 Results for Cell-Internal Faults 39 3.5.3 Results for Both Cell-External Faults and Cell-Internal Faults 39 3.5.4 Results for Open and Delay Faults in CMOS Cells 42 3.5.5 Results of Path-based Transformation Method 43 CHAPTER 4 Diagnosis-aware Pattern Generation Procedure for Various Fault Models 45 4.1 Typical Volume Diagnosis Flow and Diagnosis Patterns 45 4.2 Background 46 4.3 Diagnosis Pattern Generation for DC-Scan Fault Models 48 4.3.1 Diagnosis Pattern Generation for Stuck-at Faults 48 4.3.2 Diagnosis Pattern Generation for Bridging Faults 52 4.4 Diagnosis Pattern Generation for AC-Scan Fault Models 59 4.4.1 Diagnosis Pattern Generation for Transition Delay Faults 59 4.4.2 Diagnosis Pattern Generation between Dynamic Bridging Faults and Transition Delay Faults 68 Inverse Dynamic Bridging Faults (IDBFs) 69 4.5 Results and Comparisons 74 4.5.1 Results for Stuck-at Faults 74 4.5.2 Results for Both Stuck-at Faults and Static Bridging Faults 75 4.5.3 Comparisons of Results for Stuck-at Faults 77 4.5.4 Results for Transition Delay Faults 78 4.5.5 Results for Dynamic Bridging Faults 83 CHAPTER 5 A Repair-for-Diagnosis Methodology for Logic Circuits 86 5.1 Repairable Design at Transistor and Gate-Level 87 5.1.1 Repairable Design for a Single Transistor 87 5.1.2 Repairable Design for Standard Cells 88 5.1.3 Repair for Additional Fault Models 89 5.1.4 Use of Repair-for-Diagnosis Logic 89 5.2 Repair-for-Diagnosis Architecture 91 5.2.1 Undistinguished Fault Groups 91 5.2.2 Repair Logic Controller 92 5.3 Technologies to Optimize the Repair-for-Diagnosis Architecture 96 5.3.1 Control Vector Reduction 96 5.3.2 Use of A Decoder 97 5.3.3 Comparisons 98 5.3.4 Test Set Reduction 99 5.4 Results and Comparisons 102 5.4.1 Consideration of Distance Between Two Test-Equivalent Faults 102 5.4.2 Overall Repair-for-Diagnosis Procedure 104 5.4.3 Results without Using Distance between Faults 105 5.4.4 Results Using Distance Between Faults 108 CHAPTER 6 Conclusions and Future Work 111 6.1 Conclusions 111 6.2 Future Work 113 Reference……………………… 114 Publication List……………. 122 HONOR……………… 124

    [1] L.-T. Wang, C.-W. Wu, and X. Wen, “VLSI Test Principles and Architectures: Design for Testability,” Morgan Kaufmann, 2006.
    [2] L. M. Huisman, “Diagnosing arbitrary defects in logic designs using single location at a time (SLAT),” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., Vol. 23, No. 1, pp. 91-101, Jan. 2004.
    [3] B. Seshadri, I. Pomeranz, S. Venkataraman, M. E. Amyeen, and S. M. Reddy, “Dominance based analysis for large volume production fail diagnosis”, in Proc. IEEE VLSI Test Symp., 2006, pp. 394-399.
    [4] X. Yu and R. D. Blanton, “Diagnosis-Assisted Adaptive Test,” IEEE Trans. Computer Aided Des. Integr. Circuits Syst., Vol. 31, No. 9, pp. 1405-1416, Sep. 2012.
    [5] W. C. Tam and R. D. Blanton, “Physically-Aware analysis of systematic defects in integrated circuits,” in Proc. IEEE Int. Test Conf., 2011, pp. 1-10.
    [6] X. Fan, H. Tang, Y. Huang, W.-T. Cheng, S. M. Reddy, and B. Benware, “Improved volume diagnosis throughput using dynamic design partitioning,” in Proc. IEEE Int. Test Conf., 2012, pp. 1-10.
    [7] P.-Y. Hsueh, S.-F. Kuo, C.-W. Tzeng, J.-N. Lee, and C.-F. Wu, “Case study of yield learning through in-house flow of volume diagnosis,” in Proc. IEEE VLSI Design, Automatic and Test, 2013, pp. 1-4.
    [8] F. Hapke, J. Schloeffel, W. Redemund, A. Glowatz, J. Rajski, M. Reese, J. Rearick, and J. Rivers, “Cell-aware Analysis for Small-delay Effects and Production Test Results from Different Fault Models”, in Proc. IEEE Int. Test Conf., 2011, pp. 1–8.
    [9] F. Hapke, M. Reese, J. Rivers, A. Over, V. Ravikumar, W. Redemund, A. Glowatz, J. Schloeffel, andd J. Rajski, “Cell-aware Production Test Results from a 32-nm Notebook Process”, in Proc. IEEE Int. Test Conf., 2012, pp. 1–9.
    [10] W. Zou, W.-T. Cheng, and S. M. Reddy, “Bridge Defect Diagnosis with Physical Information”, in Proc. IEEE Asian Test Symp., 2005, pp. 248-253.
    [11] C. Liu, W. Zou, S. M. Reddy, W.-T. Cheng, M. Sharma, and H. Tang, “Interconnect Open Defect Diagnosis with Minimal Physical Information”, in Proc. IEEE Int. Test Conf., 2007, pp. 1–10.
    [12] Y. Zhang and V. D. Agrawal, “A diagnostic test generation system,” in Proc. IEEE Int. Test Conf., 2010, pp. 1-9.
    [13] J. Ye, X. Zhang, Y. Hu and X. Li, “Substantial fault pairs at-a-time (SFPAT): An automatic diagnostic pattern generation method,” in Proc. IEEE Asian Test Symp., 2010, pp. 192-197.
    [14] C.-H. Wu, K.-J. Lee, and W.-C. Lien, “An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model,” in Proc. IEEE VLSI Test Symp., 2014, pp. 1-6.
    [15] Y. Zhang and V. D. Agrawal, “Reduced complexity of test generation algorithms for transition fault diagnosis,” in Proc. IEEE Int. Conf. Comput. Des., 2011, pp. 96–101.
    [16] K.-J. Lee and C.-H. Wu, “An efficient diagnosis-aware pattern generation procedure for transition faults” in Proc. IEEE Int. Test Conf., 2014, pp. 1-10.
    [17] X. Fan, M. Sharma, W.-T. Cheng, and S. M. Reddy, “Diagnosis of Cell Internal Defects with Multi-cycle Test Patterns”, in Proc. IEEE Asian Test Symp., 2012, pp. 7-12.
    [18] H. Tang, B. Benware, M. Reese, J. Caroselli, T. Herrmann, F. Hapke, R. Tao, W.-T. Cheng, and M. Sharma, “Diagnosing Cell Internal Defects Using Analog Simulation-Based Fault Models”, in Proc. IEEE Asian Test Symp., 2014, pp. 318-323.
    [19] M. Abramovici, M. A. Breuer and A. D. Friedman, “Digital Systems Testing and Testable Design,” Computer Science Press, 1990.
    [20] F.M. Goncalves, I.C. Teixeira, and J.P. Teixeira, “Integrated Approach for Circuit and Fault Extraction of VLSI Circuits,” in Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Nov. 1996, pp. 96-104.
    [21] L.-Y. Ko, S.-Y. Huang, J.-L. Chiou, and H.-C. Cheng, “Modeling and Testing of Intra-Cell Bridging Defects Using Butterfly Structure,” in Proc. VLSI Design, Automation and Test, 2006, pp. 1-4.
    [22] P. Ohler, S. Hellebrand, and H.-J. Wunderlich, “An integrated built-in self-test and repair approach for memories with 2D redundancy,” in Proc. IEEE European Test Symp., 2007, pp. 91–96.
    [23] S.-K. Lu, C.-J. Tsai, and M. Hashizume, “Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories,” IEEE Trans. on Very Large Scale Integration Systems, Vol. 24, No. 8, pp. 2726–2734, Aug. 2016.
    [24] C.-L. Su, R.-F. Huang, C.-W. Wu, K.-L. Luo, and W.-C. Wu, “A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories,” IEEE Trans. VLSI Syst., Vol. 19, No. 12, pp. 2184-2194, Dec. 2011.
    [25] S. Kristofik and M. Balaz, “Built-in self-repair architecture generator for digital cores,” in Proc. IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016, pp. 1-6.
    [26] U. Alsaiari and R. Saleh, “Power, delay and yield analysis of BIST/BISR PLAs using column redundancy”, in Proc. Int. Symp. Quality Electron. Des., 2007, pp. 703-710.
    [27] S. Mitra, W.-J. Huang, N. R. Saxena, S.-Y. Yu, and E. J. McCluskey, “Reconfigurable architecture for autonomous self-repair”, IEEE Trans. Des. & Test of Comput., Vol. 21, No. 3, pp.228-240, May 2004.
    [28] S. Sengupta, S. Kundu, S. Chakravarty, P. Parvathala, R. Galivanche, G. Kosonocky, M. Rodgers, and TM Mak, “Defect-Based Tests: A Key Enabler for Successful Migration to Structural Test,” Intel Technology Journal, Q.1, 1999.
    [29] V. Krishnaswamy, A. B. Ma, and P. Vishakantaiah, “A Study of Bridging Defect Probabilities on a Pentium 4 CPU,” in Proc. Int. Test Conf., 2001, pp. 688-695.
    [30] D. Arumi, Rodriquez-Montanes, and J. Figueras, “Experimental Characterization of CMOS Interconnect Open Defects,” IEEE Trans. on CAD, 27(1):123–136, 2008
    [31] P. Engelke, I. Polian, M. Renovell, and B. Becker, “Automatic Test Pattern Generation for Resistive Bridging Faults,” Journal of Electronic Testing: Theory and Applications, vol. 22, no. 1, February 2006, pp. 61–69.
    [32] I. Pomeranz, “Test compaction by test cube merging for four-way bridging faults,” in Proc. VLSI Test Symp., 2015, pp. 1-6.
    [33] S. Hillebrecht, I. Polian, P. Engelke, B. Becker, M. Keim, and W.-T. Cheng, “Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model,” in Proc. Int. Test Conf., 2008, pp. 1–10.
    [34] Dominik Erb, K. Scheibler, M. Sauer, and B. Becker, “Efficient SMT-based ATPG for interconnect open defects,” in Proc. Design, Automation & Test in Europe, 2014, pp. 1-6.
    [35] F. Hapke, R. Krenz-Baath, A. Glowatz, J. Schloeffel, H. Hashempour, S. Eichenberger, C. Hora, and D. Adolfsson, “Defect-Oriented Cell-aware ATPG and Fault Simulation for industrial Cell Libraries and Designs,” in Proc. Int. Test Conf., 2009, pp.1-10.
    [36] Friedrich Hapke, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, Michael Reese, Marek Hustava, Martin Keim, Juergen Schloeffel, and Anja Fast, “Cell-Aware Test,” IEEE Trans. on CAD of Integrated Circuits and Systems, 2014, pp. 1396-1409.
    [37] Xijiang Lin, Sudhakar M. Reddy, and Janusz Rajski, “Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits,” in Proc. International Conference on VLSI Design, 2015, pp. 399-404.
    [38] G. Chen, S. Reddy, I. Pomeranz, J. Rajski, P. Engelke, and B. Becker, “A unified fault model and test generation procedure for interconnect opens and bridges,” in Proc. European Test Symp., 2005, pp. 22-27.
    [39] R. D. Blanton, “Methods for characterizing, generating test sequences for, and simulating integrated circuit faults using fault tuples and related systems and computer program products,” U.S. Patent No. 6 836 856, Dec. 28, 2004.
    [40] R.D. Blanton, Kumar N. Dwarakanath, and Rao Desineni, “Defect Modeling Using Fault Tuples,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, No. 11, Nov. 2006, pp. 2450-2464.
    [41] S. Goel and R. A. Parekhji, “Choosing the Right Mix of At-Speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency,” in Proc. Asian Test Symp., 2005, pp. 330-336.
    [42] S. Alampally, R. T. Venkatesh, P. Shanmugasundaram, R. A. Parekhji, and V. D. Agrawal, “An efficient test data reduction technique through dynamic pattern mixing across multiple fault models,” in Proc. VLSI Test Symp., 2011, pp. 285–290.
    [43] H. Konuk, “Fault Simulation of Interconnect Opens in Digital CMOS Circuits”, in Proc. Int. Conf. on Computer Aided Design, pp. 548-554, 1997.
    [44] H. Konuk, “Voltage- and Current-Based Fault Simulation for Interconnect Open Defects”, IEEE Trans. on CAD, pp. 1768- 1779, Dec. 1999.
    [45] D. Arumi, et al., “Defective Behaviors of Resistive Opens in Interconnect Lines”, in Proc. European Test Symposium, pp. 28-33, 2005.
    [46] S. Spinner, et al., “Simulating Open-Via Defects”, in Proc. Asian Test Symp., pp. 265-270, 2007.
    [47] S. Rafiq, et al., “Testing for Floating Gate Defects in CMOS Circuits”, in Proc. Asian Test Symp., pp. 228-236, 1998.
    [48] X. Lin, and J. Rajski, “Test Generation for Interconnect Opens,” in Proc. IEEE Int. Test Conf., paper 33.1, 2008.
    [49] R. L. Wadsack, “Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits,” Bell Syst. Tech. J., pp. 1449-1473, May-June 1978.
    [50] K. N. Dwarakanath, R D. (Shawn) Blanton, "Exploiting dominance and equivalence using fault tuples," in Proc. VLSI Test Symp., pp.269,274, 2002.
    [51] N. Devtaprasanna, A. Gunda, P. Krishnamurthy, S.M.Reddy, I. Pomeranz, "A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults,", in Proc. European Test Symposium, 2006. pp. 21-24.
    [52] Y. Higami et al., “Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults”, in Proc. Asian Test Symp., 2008, pp. 97-102.
    [53] Xijiang Lin, Wu-Tung Cheng and Janusz Rajski, “On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults” in Proc. Asian Test Symp., 2015
    [54] A. D. Singh, “Cell Aware and Stuck-Open Tests,” in Proc. European Test Symposium, 2016.
    [55] Y. Sato, et al., “A Persistent Diagnostic Technique for Unstable Defects”, in Proc. IEEE Int. Test Conf., pp.242-249, 2002.
    [56] I. Pomeranz and S. M. Reddy, “Diagnostic test generation based on subsets of faults,” in Proc. European Test Symposium, 2007, pp. 151-158.
    [57] I. Pomeranz and S. M. Reddy, “Output-dependent diagnositic test generation,” in Proc. Int’l Conf. on VLSI Design, 2010, pp.3-8.
    [58] V. D. Agrawal, D. H. Baik, Y. C. Kim and K. K. Saluja, “Exclusive Test and its Applications to Fault Diagnosis,” in Proc. Int’l Conf. on VLSI Design, 2003, pp. 143-148.
    [59] A. Veneris, R. Chang, M. S. Abadir, and M. Amiri, "Fault equivalence and diagnostic test generation using ATPG," in Proc. Int. Symp. Circuits and Systems, 2004, pp. 221-224.
    [60] F. Zheng, K.-T. Cheng, X. Yan, J. Moondanos and Z. Hanna, “An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability,” in Proc. IEEE Asian Test Symp., 2007, pp. 288-294.
    [61] C.-H. Wu, K.-J. Lee, W.-C. Lien, “An Efficient Diagnosis Method to Deal with Multiple Fault-Pairs Simultaneously Using a Single Circuit Model”, in Proc. IEEE VLSI Test Symp., 2014.
    [62] Y. Higami, Y. Kurose, S. Ohno, H. Yamaoka, H. Takahashi, Y. Takamatsu, Y. Shimizu, and T. Aikyo, “Diagnostic Test Generation for Transition Faults Using a Stuck-at ATPG Tool,” in IEEE Proc. Int. Test Conf., 2009. Paper 16.3.
    [63] Naresh K. Bhatti and R.D. Blanton, “Diagnostic Test Generation for Arbitrary Faults, in Proc. IEEE Int. Test Conf., pp. 1-9,” Oct. 2006
    [64] J. A. Porche and R. D. Blanton, “Physically-Aware Diagnostic Resolution,” in Proc. IEEE Asian Test Symp., 2014, pp. 206-211.
    [65] G. Eide, “Root Cause Deconvolution,” Mentor Graphics.
    [66] M. Sharma, et.al., “Layout-aware Diagnosis Leads to Efficient and Effective Physical Failure Analysis,” in Proc. Int. Symp. for Testing and Failure Analysis, 2011, pp. 1-5.
    [67] R. D. Blanton, B. Niewenhuis, and Z. Liu, “Design Reflection for Optimal Test-Chip Implementation,” in Proc. IEEE Int. Test Conf., 2015, pp. 1-10.
    [68] Z. Liu, B. Niewenhuis, S. Mittal, and R. D. Blanton, “Achieving 100% Cell-Aware Coverage by Design,” in Proc. IEEE Design, Automation Test in Europe Conference, 2016, pp. 109-114.
    [69] S. Mittal, Z. Liu, B. Niewenhuis, and R. D. Blanton, “Test chip design for optimal cell-aware diagnosability,” in Proc. IEEE Int. Test Conf., 2016, pp. 1-8.
    [70] I. Pomeranz, “Gradual diagnostic test generation and observation point insertion based on the structural distance between indistinguished fault pairs,” IEEE Trans. VLSI Syst., Vol. 20, No. 6, pp. 1026-1035, Jun. 2012.
    [71] Z. Li, S. K. Goel, F. Lee, and K. Chakrabarty, “Efficient Observation-Point Insertion for Diagnosability Enhancement in Digital Circuits,” in Proc. IEEE Int. Test Conf., 2015, pp. 1-10.
    [72] S. M. Reddy, “A Design Procedure for Fault-Locatable Switching Circuits”, IEEE Trans. on Computer, C-21, pp. 1421-1426, 1972.
    [73] J. A. Abraham and W. K. Fuchs, “Fault and error models for VLSI,” Proc. of the IEEE, Vol. 74, No. 5, pp. 639-654, May 1986.

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