成功大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	黃建輔 Huang, Chien-Fu
論文名稱：	針對延遲錯誤測試之可重置掃描鏈設計 Reconfigurable Scan Chain Design for Delay Fault Testing
指導教授：	周哲民 Jou, Jer-Min
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2006
畢業學年度：	94
語文別：	英文
論文頁數：	57
中文關鍵詞：	掃描鏈、可重置、測試、延遲錯誤
外文關鍵詞：	delay fault, testing, scan chain, reconfigurable
相關次數：	點閱：56 下載：1
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

　　對於目前深次微米的設計來說，如何加強延遲錯誤測試的錯誤涵蓋率是變得越來越重要了。在延遲錯誤測試中，一般常用的方法便是以掃描鏈為基礎的研究。雖然對於ㄧ般的電路而言，任一種掃描鏈序列皆可使錯誤涵蓋率至少達到百分之60~70，但是仍然有很大一部份的延遲錯誤依舊沒有被偵測到。因此為了得到較高的延遲錯誤涵蓋率，我們提出了一個藉由可重置化架構來實現兩種不同掃描序列的新想法。而這兩種不同掃描序列是藉由嘗試錯誤演算法來產生的。藉由我們的方法，對於大部分的序向電路而言，在硬體實現上我們只要在每個正反器之前加上一個簡單的多工器即可。而由實驗結果發現，對於大部分的測試電路，我們皆可以得到超過90%的錯誤涵蓋率。

　　Enhancing coverage for delay fault testing has becoming more important for deep sub-micron designs. The general method in delay fault testing is by scan-based approach. Although the fault coverage of general circuits can be up to at least 60~70 percent, there are still a large portions of faults which can’t be detected. The larger losses in coverage, the more risk of test-escape is induced. In order to gain higher fault coverage, we proposed a new idea that implements two different scan orders by reconfigurable architecture. We generate first scan ordering and second scan ordering with the heuristic algorithms. By our method, for most of sequential elements, we just add a simple multiplexer in hardware realization. Experimental results show the superior of this approach which demonstrates more than 90 percent fault coverage for most of circuits.

CHAPTER 1 INTRODUCTION..................................................1
　1.1 Delay Test Problem................................................2
　1.2 Delay Fault Model and Basic Methodology ..........................3
　1.2.1 Path Delay Fault ...............................................3
　1.2.2 Transition Fault ...............................................3
　1.2.3 Basic Methodology ..............................................4
　1.3 Motivation .......................................................6
　1.4 Thesis Organization...............................................6
CHAPTECHAPTER 2 RELATED WORKS ..........................................7
　2.1 Skewed-load Approach .............................................8
　2.2 Broad-side Approach...............................................8
　2.3 Hybrid Approach ..................................................9
　2.4 Distance Restricted Approach .....................................10
CHAPTER 3 FAULT CATEGORIES AND CLASSES..................................11
　3.1 Detected Faults (DT) .............................................12
　3.2 ATPG Untestable Faults (AU).......................................12
　3.3 Not Detected Faults (ND) .........................................13
　3.4 Undetectable Faults (UD)..........................................13
CHAPTER 4 IMPLEMENTATION OF RECONFIGURABLE SCAN.........................16
　4.1 Problem Formulation...............................................17
　4.2 Data Structure....................................................18
　4.3 Design Flow ......................................................20
　4.4 First Scan Chain .................................................22
　　4.4.1 Building the First Type Logic Cone Matrix ....................22
　　4.4.2 Generating the Fist Scan Chain................................25
　4.5 Second Scan Chain.................................................26
　　4.5.1 Building the Second Type Logic Cone Matrix....................26
　　4.5.2 Generating the Second Scan Chain .............................29
　4.6 Special Case .....................................................31
　4.7 Time and Space Complexity ........................................32
　　4.7.1 Time Complexity...............................................32
　　4.7.2 Space Complexity .............................................32
　4.8 The Implementation of Our Design..................................33
CHAPTER 5 EXPERIMENTAL RESULTS .........................................36
　5.1 Results Analysis .................................................37
　5.2 Comparison and Discussion.........................................42
　　5.2.1 Comparing Results with Three Methods..........................42
　　5.2.2 Comparing Results with Distance Restricted Approach ..........45
　5.3 An Operating Example .............................................47
CHAPTER 6 CONCULSION AND FUTURE WORK....................................54
　6.1 Conclusion........................................................54
　6.2 Future Work.......................................................55
REFERENCE...............................................................56
                                    

[1] J. Savir and S. Patil, “On Broad-Side Delay Test”, Proc. VTS, pp. 284-290, Sept. 1994.
[2] J. Savir and S. Patil, “Scan-Based Transition Test”, IEEE TCAD, pp. 1232-1241, August 1993.
[3] S. Wang, X. Liu and S. T. Chakradhar, “Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets”, Proc. DATE, pp. 1296-1301, 2004.
[4] Wei Li; Seongmoon Wang; Chakradhar, S.T.; Reddy, S.M, “Distance restricted scan chain reordering to enhance delay fault coverage”, IEEE VLSID pp.471-478, 2005.
[5] J. A. Waicukauski, E. Lindbloom, B. K. Rosen and V. S. Iyengar, “Transition Fault Simulation”, IEEE Design & Test of Computers, Vol. 4, No.2, April 1987.
[6] B. Dervisoglu and G.. Stong, “Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement”, Proc. ITC, pp.365-374, 1991.
[7] Synopsys, “TetraMax User Guide”.
[8] Vishwani D. Agrawal, “ Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI circuits”, 2000.
[9] Manish Sharma, “Enhancing Defect Coverage of VLSI Chips by Using Cost Effective Delay Fault Tests”, Phd, University of Illinois at Urbana-Champaign, 2003
[10] V. S. Iyengar. B. K. Rosen, and I. Spillinger, “Delay test generation I. concepts and coverage metrics.” in proceedings of the International Test Conference, 1988, pp. 857-866.
[11] A. K. Pramanick and S. M. Reddy, “On the detection of delay faults.” in proceedings of the International Test Conference, 1988, pp. 845-856.
[12] J. A. Waicukauski, E. Lindbloom, B. K. Rosen, and V. S. Iyenger, “Transition fault simulation.” IEEE Design & Test of Computers, vol.4 no. 2. pp.32-38, April 1987.
[13] G. L. Smith, “Model for delay faults based upon paths,” in proceedings of the International Test Conference, 1985, pp. 342-349.
[14] J. Saxena, K. M. Butler, J. Gatt, R. R, S. P. Kumar, S. Basu, D. J. Campbell, and J. Berech. Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges. In Proceedings IEEE International Test Conference, pages 1120–1129, 2002.

校內：2007-08-25公開
校外：2010-08-25公開

簡易檢索 / 詳目顯示

相關論文