隨著無線網路佈建之日臻成熟，對於移動式多媒體的需求亦愈形迫切。而為了在有限的頻寬內，傳送高品質的視訊畫面，高效率的壓縮技術已被視為重要之解決方案，也因此國際電信聯盟的電信標準化部門提出H. 264的視訊標準，確有助於大幅降低所需的傳送頻寬，而本文即針對此項標準提出專用電路以滿足即時視訊的要求。
　　目前相關視訊標準的運算架構日趨繁複，傳統的純邏輯電路的實現方式已力有未逮，而現階段的晶片設計更已逐漸邁向系統晶片(System-on-a-Chip; SoC)的設計理念，透過軟/硬體的協同設計使得晶片可同時兼顧彈性與運算效能。然而複雜的晶片設計，卻將對驗證與除錯的工作形成極嚴峻的挑戰。因此本研究亦提出以周邊元件互連匯流排(PCI)為輔的測試平台，期能經由資料傳輸效能之改進，達成有效驗證評估的目的。
　　另為佐證本研究之可行性，本文在實作中將以軟/硬體協同設計的方式完成H. 264的視訊編碼晶片，同時在設計中嵌入PCI的橋接器以供測試與驗證所需，此外並將本研究中所提出之H. 264晶片，全以場規劃邏輯閘陣列 (Field Programmable Gate Array; FPGA)予以實現，且經由視訊資料予以驗證，測試結果證實本文所提之架構及其實作設計應已具有高度實用價值。

　　With the advent of wireless network, the demand of mobile multimedia information has become an urgent issue. To deal with such a situation, a novel compression approach of H. 264 Specification has been proposed to provide a more efficient way of delivering video information even under a bandwidth-limited wireless network environment. However, the complexity of this specification was seen more than that of other standards; hence, motivating the application of dedicated hardware to conquer this computing bottleneck while satisfying the high compression performance requirements.
　　In this thesis, considering to handling the increasing complexity revealed by the specification, the chip design is also gradually focused on the hardware/software co-design chip rather than the hardware-only logic circuit. In other words, the concept of the system-on-a-chip (SoC) was also embedded into the whole design. Then, by taking the burden reduction of verification and debug tasks into consideration, a novel idea in anticipation of reaching the construction of a verification environment with higher bandwidth and shorter response time is also completed. Namely, the peripheral component interconnection (PCI) bus was effectively included in the verification of SoC, where PCI bridge circuits along with a general-purpose processor were also designed in full cooperation such that the validation of the completed H. 264 IP can be well accomplished.
　　Besides, in order to validate the effectiveness of the study, a hardware and software co-design methodology is employed for the implementation of H. 264 compression kernel. Furthermore, the H.264 chip is fully realized with the aid of field programmable gate array (FPGA) and tested through the video clip data. From the test results, they help support the proposed method for the applications considered.

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