本論文提出多項用於次區間式類比/數位轉換技術，以實現高速低功耗。
針對高速低功耗類比/數位轉換器設計，本論文提出使用嵌入式參考電壓比較器之次區間式類比/數位轉換器。透過調整嵌入式參考電壓比較器之偏壓電流或基體電壓，偏移誤差可調整成特定的電壓，稱為嵌入式參考電壓。在第一級中，比較器利用偏壓電流實現寬範圍之嵌入式參考電壓。在第二級中，窄範圍之嵌入式參考電壓由基體電壓實現。此外，透過第一級輸出結果調整第二級的偏壓電流可調整第二級所需的次區間電壓。因此本類比/數位轉換器與傳統方式比不需要參考電壓切換網路，可大幅提升操作速度。本論文使用一電阻階梯來校正偏移誤差，校正完畢後即移除該電阻階梯，因此可大幅降低功率消耗。本論文使用28nm CMOS製程實現一3mW 6位元 4GS/s次區間式類比/數位轉換器，在輸入高頻時，開啟校正後SNDR各自可達到30.7dB在4GS/s及31.8dB在3.6GS/s。其中在3.6GS/s操作時，本論文與現有6至8位元類比/數位轉換器相比有最佳效能指標FoMW。
為了實現高速及更高的解析度，本論文另外提出極性偵測技術實現一嵌入式參考電壓比較器之次區間式類比/數位轉換器。該極性偵測技術可藉由輸入訊號判斷類比/數位轉換器的MSB訊號。藉由將次區間式類比/數位轉換器分割成兩個子類比/數位轉換器及極性偵測結果，每次比較只需要激活其中一個子轉換器，因此可節省接近一半的功率消耗。此外，由於極性偵測與取樣電路是同時進行，不需要額外的運作步驟，因此可維持原本次區間式類比/數位轉換器兩個步驟之高速運作。本論文使用28nm CMOS製程實現一5.1mW 8位元 3GS/s次區間式類比/數位轉換器。本論文與現有最佳文獻相比有最佳效能指標FoMW。

In this dissertation, several techniques are proposed for subranging analog-to-digital converters (ADCs) to achieve high speed and low power consumption.
To design a high-speed low-power ADC, a subranging ADC with reference-embedded comparators (RECs) is proposed. By adjusting the bias current and/or body voltage of the REC’s input differential pair, the REC offset can be adjusted to a specific voltage equal to a reference voltage referred to henceforth as the embedded reference. For the ADC’s coarse stage, RECs with wide-range embedded references are implemented by adjusting the bias currents using current source arrays to cover the full-scale input. By contrast, for the ADC’s fine stage, RECs with narrow-range embedded references are implemented by adjusting the body voltage. In addition, the centers of the embedded references in the different ADC subranges are created by current source arrays, which are digitally scaled according to the coarse ADC’s output codes. As a result, the reference-voltage-switching network used in conventional subranging ADCs is not required, and hence the speed of the ADC is increased. Moreover, to eliminate the effects of process variation, the bias currents and body voltages in the RECs are calibrated with an auxiliary resistor ladder. After the calibration, the resistor ladder is removed. Consequently, no resistor ladder is used during normal operation, which greatly saves power. A 3mW 6-bit 4GS/s REC-based subranging ADC is implemented in 28-nm CMOS technology. With a near Nyquist frequency input, the ADC achieves SNDRs of 31.8dB and 30.7dB at 3.6GS/s and 4GS/s, respectively. Moreover, at 3.6GS/s, the ADC has a Walden Figure-of-Merit (FoMW) of 22.7fJ/conv-step, which is the best compared with prior state-of-the-art 6-8 bit high-speed ADCs.
To achieve a high-speed ADC with higher resolution, REC-based subranging ADC with polarity detection technique is proposed. With the proposed polarity detection technique, the differential input polarity can be detected to determine the most significant bit (MSB) of the ADC. Thus, the subranging ADC can be divided into two spilt sub-ADCs and hence only the corresponding sub-ADC is enabled in each conversion to save power. In addition, the input signal is tracked and detected respectively by the polarity detection circuit and track-and-hold circuit simultaneously. Thus, the ADC maintains the high speed operation without additional operation step. A 5.1 mW 8-bit 3 GS/s REC-based subranging ADC is implemented in 28 nm CMOS technology. With a near Nyquist frequency sine-wave input, the ADC achieves an SNDR of 43.8 dB at 3 GS/s, which results in the Walden Figure-of-Merit (FoMW) of 13.4 fJ/conv-step. which is the best compared with prior state-of-the-art high-speed ADCs.

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