亂序執行處理器架構與if-conversion，這兩項對於增進程式執行效率都是非常普遍且重要的技術。If-conversion可以有效減少程式碼中條件分支的使用，降低分支預測錯誤懲罰對效能的影響，在一般管線處理器中可以得到很大的好處。但是當亂序執行處理器執行if-conversion所轉換出來的程式時，會發生暫存器重覆命名的問題。這是個必須要解決的問題，否則處理器將無法正確的執行指令。若是消極地暫停處理器管線，避免錯誤的情況發生，反而會造成效能低落。
在這篇論文中，我們基於ARM指令集架構的特性，設計一個預測條件旗標的機制與硬體架構，我們動態儲存指令最近幾次寫入條件旗標的歷史紀錄，並設計一個條件旗標的選擇機制從歷史紀錄中選擇最有可能的旗標作為預測結果。這個方法解決了暫存器重覆命名的問題。並且平均有5.89%的效能增益。

In high-performance processor architecture, out-of-order execution and if-conversion are two very common techniques for performance improvement. If-conversion is a compiler technique that reduces the misprediction penalties caused by conditional branches. Using if-conversion on the out-of-order execution architecture creates a register naming problem. If there are multiple updates of the same register of different conditions and if the condition flags have not been resolved, then it is unknown which physical register should be mapped on to the architectural register. To deal with this problem, one approach could simply stall the renaming unit until the condition flag is resolved, however this would cause great performance degradation.
Predicting condition flag is an effective approach to address this problem. In this thesis, we propose a new scheme to predict the condition flag based on the ISA of ARM. By storing two most recent unique condition flag values for each instruction dynamically in the run time, and by using a condition flag selector when a condition flag-updating instruction reaches the renaming unit, we can predict the outcome of the condition flag-updating instruction. The approach enables an efficient implementation of if-conversion for our out-of-order processor to deal with the multiple definition problem.
To design the condition flag predictor, we use the concept of branch prediction to implement our flag selector and we combine a threshold value to the basic condition flag prediction mechanism. We have simulated benchmark programs in different threshold value and have evaluated a popular branch predictors in our flag selector. We show that our approach is able to achieve an IPC performance increase of 5.89%.

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