隨著半導體製程的進步及尺寸微縮，電晶體微縮過程中遭遇了嚴重的短通道效應，使用多閘極結構藉由增加閘極控制能力為其中一種改善短通道效應的方法。而鰭式場效應電晶體為目前為廣泛應用於半導體工業製造中的元件。然而在傳統矽晶圓上製作鰭式場效應電晶體時需透過高強度的電漿蝕刻以及沉積絕緣氧化層來控制鳍高，在此過程中會產生介面氧化層電荷堆積在矽及二氧化矽的表面，造成元件特性下降。
在本篇論文中，我們透過元件量測以及三維數值模擬軟體成功校正出元件電容-電壓(C-V)與電壓-電流(I-V)之電氣特性，從C-V曲線中，可以計算出等效氧化層厚度(EOT)並代回元件模擬中，接著，由I-V曲線可得到介面氧化層電荷密度。
為了進一步了解介面氧化層電荷對元件的影響，在論文中考量了不同參數對鰭式場效應電晶體的影響。結果顯示在寬的鰭寬(fin width)、濃的基板濃度摻雜(substrate doping)、越淺的源極及汲極摻雜介面深度(junction depth)以及適當的抗撃穿阻擋層深度(punch through stopper layer depth)在有高濃度的介面氧化層電荷存在時可以有效減少漏電流的大小，改善次臨界擺幅(subthreshold swing, SS)以及汲極引致能障下降(drain-induced barrier lowering, DIBL)，而在通道下方進行氧離子佈植並氧化成氧化層可最有效阻絕漏電流的產生，得到最好的介面氧化層電荷免疫效果。

With the progress of semiconductor process and device scaling, there is serious short channel effect when proceeding the scaling of transistors. Increasing the gate controllability by multi gate structure is one of methods to improve the short channel effect. FinFETs has been widely applied and used for manufacturing CMOS devices in the semiconductor industrial field. However, while manufacturing FinFETs on the bulk silicon wafer, it is necessary to control the fin height by high intensity plasma etching and deposition of insulating oxide layer. The interface oxide charge is thus produced at the interfacial region between silicon and oxide in this process, which cause degrading of device performance.
In this thesis. We calibrate successfully the electrical performance of device, such as capacitance-voltage (C-V) and current-voltage (I-V) by measurements of devices and three dimensional mathematical simulation software. From the C-V curve, equivalent oxide thickness (EOT) can be calculated and then the extracted EOT could be substituted into device simulation. From the I-V curve, the charge density of interface oxide layer can be obtained.
In order to further investigate the influence of interface oxide charge on devices, we consider the impact of different parameters on FinFETs. The simulated results show that wide fin width, heavy substrate doping, shallow junction depth and proper punch through stopper layer depth tend to effectively reduce the leakage current when high interface oxide charge density and thus degraded subthreshold swing (SS) and drain-induced barrier lowering (DIBL) have occurred. By using oxygen ion implantation under the channel and further oxidation into oxide layer, it is found to be the most effective method to inhibit leakage current.

[1] X. Hiao, Introduction to semiconductor manufacturing technology: Prentice Hall, 2000.
[2] G. E. Moore, "Cramming more components onto integrated circuits," Proceedings of the IEEE, vol. 86, pp. 82-85, 1998.
[3] P. M. Zeitzoff, J. A. Hutchby, G. Bersuker, and H. R. Huff, "Integrated circuit technologies: from conventional CMOS to nanoscale era," Nano and Giga Challenges in Microelectronics, pp. 1-25, 2003.
[4] K. J. Kuhn, "CMOS scaling for the 22nm node and beyond: Device physics and technology," in VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on, 2011, pp. 1-2.
[5] M. Ieong, B. Doris, J. Kedzierski, K. Rim, and M. Yang, "Silicon device scaling to the sub-10-nm regime," Science, vol. 306, pp. 2057-2060, 2004.
[6] E. Vogel, "Technology and metrology of new electronic materials and devices," Nature nanotechnology, vol. 2, pp. 25-32, 2007.
[7] J.-T. Park and J.-P. Colinge, "Multiple-gate SOI MOSFETs: device design guidelines," IEEE Transactions on Electron Devices, vol. 49, pp. 2222-2229, 2002.
[8] Y. Taur and T. H. Ning, Fundamentals of modern VLSI devices: Cambridge university press, 2013.
[9] S. M. Sze, Semiconductor devices: physics and technology: John Wiley & Sons, 2008.
[10] A. Cherian, A. Augustine, J. Jose, and V. Pangracious, "A Novel Methodology For Thermal Analysis & 3-Dimensional Memory Integration," arXiv preprint arXiv:1109.0708, 2011.
[11] I. Ferain, C. A. Colinge, and J. P. Colinge, "Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors," Nature, vol. 479, pp. 310-6, Nov 16 2011.
[12] J.-P. Colinge, FinFETs and other multi-gate transistors vol. 73: Springer, 2008.
[13] A. R. Brown, N. Daval, K. K. Bourdelle, B.-Y. Nguyen, and A. Asenov, "Comparative simulation analysis of process-induced variability in nanoscale SOI and bulk trigate FinFETs," IEEE Transactions on Electron Devices, vol. 60, pp. 3611-3617, 2013.
[14] K. Goodson, Y. Leung, and S. Wong, "Temperature-dependent thermal conductivity of single-crystal silicon layers in SOI substrates," 1998.
[15] J. G. Fossum, Z. Zhou, L. Mathew, and B.-Y. Nguyen, "SOI versus bulk-silicon nanoscale FinFETs," Solid-State Electronics, vol. 54, pp. 86-89, 2010.
[16] R. Li, Y. Liu, K. Zhang, C. Zhao, H. Zhu, and H. Yin, "Punch through stop layer optimization in bulk FinFETs," in Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on, 2014, pp. 1-3.
[17] R. Deshmukh, A. Khanzode, S. Kakde, and N. Shah, "Compairing FinFETs: SOI Vs Bulk: Process variability, process cost, and device performance," in Computer, Communication and Control (IC4), 2015 International Conference on, 2015, pp. 1-4.
[18] B. E. Deal, "Standardized terminology for oxide charges associated with thermally oxidized silicon," IEEE Transactions on Electron Devices, vol. 27, pp. 606-608, 1980.
[19] B. Kim, D.-I. Bae, P. Zeitzoff, X. Sun, T. E. Standaert, N. Tripathi, et al., "Investigation of fixed oxide charge and fin profile effects on bulk FinFET device characteristics," IEEE Electron Device Letters, vol. 34, pp. 1485-1487, 2013.
[20] C. Hu, Modern semiconductor devices for integrated circuits: Prentice Hall, 2010.
[21] S. S. K. Iyer, X. Lu, J. Liu, J. Min, Z. Fan, P. K. Chu, et al., "Separation by Plasma Implantation of Oxygen (SPIMOX) operational phase space," IEEE transactions on plasma science, vol. 25, pp. 1128-1135, 1997.
[22] Sentaurus Device, User Guide, Synopsys Inc. ver. G-2012.06, June 2012.