隨著製程技術與設計自動化工具的快速演進，越來越多大型且複雜的電路被整合進系統單晶片。針對矽晶片除錯技術中，運作中停下並恢復除錯方法能藉由將電路停下時脈，並透過測試架構中的掃描練擷取電路內部暫存器狀態供使用者觀察，再將電路時脈恢復用以進行下一步的除錯流程。資料無效是使用此多時域除錯技術時可能會發生並且需注意的問題。包含跨時域數據傳輸介面的除錯系統，可在任一時脈週期暫停電路並且可避免捕捉到錯誤的數據。在本論文中，我們以成大測試實驗室所開發的單晶片系統除錯平台為基礎，致力於將此除錯平台與業界實際環境整合。將此除錯平台整合至業界的系統單晶片環境之後，再以業界實際的矽智產電路做為除錯對象，並實現在業界的雛型驗證版上。我們也將此平台與跨時域數據傳輸介面的除錯系統結合，提出嶄新的除錯流程，使除錯功能更加完整。此外，我們亦結合使用者圖形介面來與此除錯平台共同運作，提供使用者設定與顯示除錯點的結果，以判別實際晶片中錯誤的根本原因。實驗結果顯示所開發的除錯平台應用到業界實際電路的可行性，能有效地解決晶片的除錯問題，加速業界產品的開發過程。

With the rapid development of semiconductor technology and design automation tools, more and more designs are now integrated into a system-on-chip (SoC). The run-pause-resume silicon debug approach allows users to pause the normal (system) operations of the circuits under debug (CUDs), extract the internal states of the CUDs for examination, and then resume the normal operations for further debugging. Data invalidation is the main problem that needs to be faced in the multiple-clock-domain design with this methodology. A RPR technique that with a Clock-Domain-Crossing (CDC) interface can avoid data invalidation with the cycle-level granularity of debugging resolution.
In this thesis, we integrate the SoC debug platform developed by the NCKU Test Lab with a real industrial SoC design environment. After the integration, we employ an actual industrial intellectual property (IP) core as the core under debug and then implement the whole SoC system on board. We also combine the debug platform with the multiple-clock-domain system, and propose novel debug procedures which make the debugging functions complete system and efficient. Furthermore, we combine a graphic user interface to support set the breakpoint and display which allows users to observe the results of hardware easily to identify the root-cause of failures in the real chip. Experimental results show that the implement debugs technology deals with the chip debugging problems efficiently.

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