在本論文中實現了一個具有數位頻率調變演算法的時脈展頻器(spread spectrum clock generator)。組成這個時脈展頻器的主要電路有200MHz的鎖相迴路、資料佇列和數位頻率調變器。傳統的頻率調變的方式都是三角波輸入到壓控震盪器做調變，這個方式所實現的時脈展頻器通常都應用在產生系統時脈訊號。在本論文中的時脈展頻器是用來同時對系統時脈與系統資料做展頻，且展頻後的資料是與展頻後的系統時脈同步，用來降低在資料傳送上的電磁效應。為了符合這個應用，本論文使用了一個演算法。在這演算法中，會由偵測輸入時脈與調變後時脈的相位差來產生三角調變波。這個方法的特點是它會將最大的累積相位差控制在演算法所設定的量以下。控制相位差的目地是使得資料在資料佇列中正確的傳送。因此，這個時脈展頻器不但能對系統時脈做調變，還能使得展頻後的資料與展頻後的統時脈同步。

This thesis implements a spread spectrum clock generator (SSCG) with new algorithm of digital frequency modulation. The spread spectrum clock generator is composed of 200MHz phase look loop (PLL), parallel data queue, and digital frequency modulator. Conventional method of generating spread-spectrum clock is that modulating voltage controlled oscillator (VCO) directly by a triangular wave with a constant modulation frequency. Common application of spread-spectrum technique is mainly in the generation of system clock signals. In this thesis, this SSCG is utilized for spreading both clock signals and the data in spectrum for reducing EMI when these signals are transmitted on transmission line. These data are simultaneously synchronized by the clock signals. To match this new application, a new algorithm of implementing spread spectrum clock generator is proposed. In this algorithm, the triangular wave is generated by detecting phase error of two clock signals, which are input reference clock and the clock generated by VCO, respectively. The major characteristic of using this technique is that controlling the phase error of two clock signals smaller than a value decided by algorithm of digital frequency modulation. The phase error controlled is used to keep the data of parallel data queues transmitted correctly. Therefore, the SSCG can not only generate a spread spectrum clock but also control the data sequence synchronized by the clock in parallel data queues.
This SSCG is fabricated in 0.25μm 1P5M CMOS technology and occupies an area of 1.05mm x 1.08mm. By simulation, the power consumption is 42mW at 2.5 supply voltage and the spread rate is 12% at 200MHz center frequency. The amplitude is attenuated about 15dB at the spectrum analysis

[1]“IEEE standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI)” IEEE Std 1596.3-1996 , 31 Jul 1996
[2]Joungho Kim”Solution space analysis of interconnects for low voltage differential signaling (LVDS) applications” Electrical Performance of Electronic Packaging, 2001
[3]Y. Lee and R. Mittra “Electromagnetic Interference Mitigation by Using a Spread-Spectrum Approach” IEEE Transaction on electromagnetic compatibility, VOL. 44, NO. 2, MAY 2002
[4]K. B. Hardin, J. T. Fessler, and D. R. Bush, “Spread-spectrum clock generation for the reduction of radiated emissions,” in Proc. IEEE Int. Symp. Electromagnetic Compatibility, 1994, pp. 227–231.
[5]J. Y. Michel and C. Neron, “A frequency modulated PLL for EMI reduction in embedded application,” in Proc. IEEE Int. ASIC/SOC Conf.,1999, pp. 362–365.
[6]M. Sugawara et al., “1.5-Gb/s 5150-ppm spread-spectrum SerDes PHYwith a 0.3-mW 1.5-Gb/s level detector for serial ATA,” in Symp. VLSI Circuits Dig. Tech. Papers, June 2002, pp. 60–63.
[7]H. S. Li, Y. C. Cheng, and D. Puar, “Dual-loop spread-spectrum clockgenerator,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers,1999, pp. 184–185.
[8]Y. Moon, D. K. Jeong, and G. Kim, “Clock dithering for electromagnetic compliance using spread-spectrum phase modulation,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 1999, pp. 186–187.
[9]H. W. Chen and J. C. Wu, “A spread-spectrum clock generator for EMI reduction,” IEICE Trans. Electron., pp. 1959–1966, Dec. 2001 [10]H. Mair and L. Xiu, “An architecture of high-performance frequency and phase synthesis,” IEEE J. Solid-State Circuits, vol. 35, pp. 835–846, June 2000.
[10] E. Albuquerque and M. Silva “A New Low-Noise Logic Family for Mixed-Signal Integrated Circuits” in IEEE Transactions on Circuits And Systems—I: Fundamental Theory and Applications, Vol. 46, NO. 12, DECEMBER 1999
[11]B. Razavi , “Monolithic Phase-Locked Loops And Clock Recovery Circuits” IEEE 1996.
[12] B. Razavi ,“Design of Analog CMOS Integrated Circuits” 2001
[13]D.H. Wolaver, “Phase-Locked Loop Circuit Design” Englewood Cliffs, NJ : Prentice-Hall,1991
[14]S. Kim et al., “A 960-Mb/s/pin interface for skew-tolerant bus using low-jitter PLL,” IEEE J. Solid-State Circuits, vol. 32, pp. 691–700, May 1997.
[15]F. Lin and D. Chen, “Reduction of power supply EMI emission by switching frequency modulation,” IEEE Trans. Power Electron., vol. 9,pp. 132–137, Jan. 1994.
[16]R. C. Dixon, “Spread Spectrum Systems”. New York, NY: Wiley, 1984.
[17]K. B. Hardin, J. T. Fessler, and D. R. Bush, “Spread spectrum clock generation for the reduction of radiated emissions,” in Proc. IEEE Int. Symp. Electromagnetic Compatibility, 1994, pp. 227–231.
[19]T.Y. Hsu, B.J. Shieh and C.Y. Lee “An All-Digital Phase-Locked Loop (ADPLL)-Based Clock Recovery Circuit” IEEE J. Solid-State Circuit, vol 34, NO 8, August 1999.
[20]B. Chun, Y. Lee, and B. Kim, “Design of variable loop gain of dual-loop DPLL,” IEEE Trans. Commun., vol. 45, pp. 1520–1522, Dec. 1997. P. F. Driessen, “DPLL bit synchronizer with rapid acquisition using adaptive Kalman filtering techniques,” IEEE Trans. Commun., vol. 452,pp. 2673–2675, Sept. 1994.
[21]B. Kim, “Dual-loop DPLL gear-shifting algorithm for fast synchronization,”
IEEE Trans. Circuits Syst. II, vol. 44, pp. 577–586, July 1997.
[22]T. H. Hu and P. R. Gray, “A monolithic 480 Mb/s parallel AGC decision clock-recovery circuit in 1.2um CMOS,” IEEE J. Solid-State Circuits, vol. 28, pp. 1314–1320, 1993.
[23]J. Lee and B. Kim, “A 250 MHz low jitter adaptive bandwidth PLL,” in Proc. IEEE Int. Solid-State Circuits Conf., 1999, pp. 346–347.
[24]A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, pp. 179–195, Feb.1998.
[25]K. Iravani, F. Saleh, D. Lee, P. Fung, P. Ta, and G. Miller, “Clock and data recovery for 1.25 Gb/s Ethernet transceiver in 0.35 um CMOS,” in Proc. Custom Integrated Circuits Conf., 1999, pp. 261–264.
[26]V. von Kaenel, D. Aebisher, C. Piguet, and E. Dijkstra, “A 320 MHz, 1.5 mW at 1.35 V CMOS PLL for microprocessor clock generation,” in Proc. IEEE Int. Solid-State Circuits Conf., 1996, pp. 132–133.
[27]J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, pp.1723–1732, Nov. 1996.
[28]F. M. Gardner, “Charge-pump phase-lock loops,” IEEE Trans. Communications,
vol. COM-28, pp. 1849–1858, Nov. 1980.
[29]M. Johnson and E. Hudson, “A variable delayline PLL for CPU coprocessor synchronization,” IEEE J. Solid-State Circuits, vol. SC-23, pp. 1218–1223, Oct. 1988.
[30]P. Larsson and J.-Y. Lee, “A 400 mW 50–380 MHz CMOS programmable clock recovery circuit,” in Proc. IEEE ASIC Conf. Exhibit, 1995, pp. 271–274.
[31]P. Larsson, “A 2–1600 MHz 1.2–2.5 V CMOS clock-recovery PLL with feedback phase-selection and averaging phase-interpolation for jitter reduction,” in Proc. IEEE Int. Solid-State Circuits Conf., 1999, pp. 356–357.
[32]J. F. Ewen et al., “Single-chip 1062 Mbaud CMOS transceiver for serial data communication,” in Proc. IEEE Int. Solid-State Circuits Conf., 1995, pp. 32–33.
[33]A. Hajimiri, S. Limotyrakis, and T. H. Lee, “Jitter and phase noise in ring oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 790–804, June 1999.
[34]I. Novof, J. Austin, R. Chmela, T. Frank, R. Kelkar, K. Short, D. Strayer, M. Styduhar, and S. Watt, “Fully-integrated CMOS phase-locked loop with 15–240 MHz locking range and 50 ps jitter,” in Proc. IEEE Int. Solid-State Circuits Conf., 1995, pp. 112–113.
[35]Z. X. Zhang, H. Du, and M. S. Lee, “A 360 MHz 3 V CMOS PLL with 1 V peak-to-peak power supply noise tolerance,” in Proc. IEEE Int. Solid-State Circuits Conf., 1996, pp. 134–135.
[36]I. A. Young, M. F. Mar, and B. Bhushan, “A 0.35 um CMOS 3–880 MHz PLL N/2 clock multiplier and distribution network with low jitter for microprocessors,” in Proc. IEEE Int. Solid-State Circuits Conf., 1997, pp. 330–331.
[37]A. Demir, A. Mehrotra, and J. Roychowdhur, “Phase noise in oscillators: A unifying theory and numerical methods for characterization,” in Proc. ACM/IEEE Design Automation Conf., June 1998, pp. 26–31.
[38]P. Kinget, “Integrated GHz voltage controlled oscillators,” in Proc. Advances in Analog Circuit Design, Nice, France, Mar. 1999.
[39]S. Radu, M. Li, J. Nuebel, D. Hockanson, Y. Ji, J. L. Drewniak, T. H. Hubing, and T. P. Van Doren, “Investigation of internal partitioning in metallic enclosure for EMI control,” in Proc. IEEE Int. Symp. Electromagnetic Compatibility, 1997, pp. 171–176.
[40]K. B. Hardin, N. L. Webb, J. B. Berry, A. L. Cable, and M. J. Pulley,“Design considerations of phase-locked loop systems for spread spectrum clock generation compatibility,” in Proc. IEEE Int. Symp. Electromagnetic Compatibility, 1997, pp. 302–307.
[41]H.H. Chang, I.H. Hua and S.I. Liu “A Spread-Spectrum Clock Generator With Triangular Modulation” in IEEE Journal of Solid-State Circuits, VOL. 38, NO. 4, APRIL 2003.
[42]D.J. Allstot, G. Liang, H.C. Yang “Current-Mode Logic Techniques for CMOS Mixed-Mode ASIC” in CICC,pp,2521-2524,1991
[43]D. J. Allstot, S. Kiaei, and R. H. Zele, “Analog logic techniques steer around the noise,” IEEE Circuits Devices Mag., vol. 9, pp. 18–21, Sept.1993.
[44]H.-T. Ng and D. J. Allstot, “CMOS current steering logic for low-voltage mixed-signal integrated circuits,” IEEE Trans. VLSI Syst., vol. 5, pp. 301–308, Sept. 1997.
[45]K. B. Hardin, J. T. Fessler, and D. R. Bush, “Spread spectrum clock generation for the reduction of radiated emissions,” Proc. 1994 IEEE Int. Symp. Electromagnetic Compatibility, pp. 227–231, Aug. 1994.
[46]“Spread Spectrum Clock Generation TV Interference Study,” Philips Consumer Electronics Company, Knoxville, TN, Tech. Rep. T43 111–2, 1994.
[47]K. B. Hardin, J. T. Fessler, and D. R. Bush, “A study of the interference potential of spread spectrum clock generation techniques” Proc. 1995 IEEE Int. Symp. Electromagnetic Compatibility, pp. 624–629, Aug.1995.
[48]H. G. Skinner and K. P. Slattery, “Why spread spectrum clocking of computing device is not cheating,” Proc. 2001 IEEE Int. Symp. Electromagnetic Compatibility, vol. 1, pp. 537–540, Aug. 2001.