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研究生：	趙億智 Chao, Yi-Chih
論文名稱：	多標準反轉換與H.264/AVC視訊解碼核心架構設計 Architecture Designs for H.264/AVC Decoder Kernel with Multi-Standard Inverse Transforms
指導教授：	劉濱達 Liu, Bin-Da
共同指導教授:	楊家輝 Yang, Jar-Ferr
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2011
畢業學年度：	99
語文別：	英文
論文頁數：	109
中文關鍵詞：	H.264/AVC 、VC-1 、AVS 、VLSI 、CAVLC 、量化、離散餘弦轉換 (DCT)
外文關鍵詞：	H.264/AVC, VC-1, AVS, VLSI, CAVLC, Quantization, Discrete Cosine Transform (DCT)
相關次數：	點閱：104 下載：1
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ITU-T VCEG和ISO/IEC MPEG所提出的H.264/AVC、微軟的VC-1和中國的AVS為目前最熱門視訊壓縮標準。為了解碼H.264/AVC 標準中的殘值，整個架構需要CAVLC解碼器、反量化器、反轉換器。在硬體設計上，因為這些元件的解碼速度不同，在元件之間的介面必須很小心的設計來緩衝它們之間的資料傳輸。為了有效的實現 CAVLC 解碼器和反量化器之間的介面，本論文分析了在H.264/AVC 標準中的解碼流程。在適當的安排CAVLC 解碼器和反量化器的解碼流程後，所提出的架構只需要一個反量化器，而且更進一步將它整合到CAVLC 解碼器中來減少緩衝器的面積。另一方面，此研究也針對H.264/AVC視訊標準提出了低成本的反轉換架構。
目前有越來越多的消費性產品能支援多種視訊壓縮格式，如何去設計出能支援多種標準的硬體是很重要的。為了實現低成本的硬體設計，本論文也提出了一個應用於多個標準的整合性反轉換架構，此架構能有效地被使用於H.264/AVC，VC-1以及AVS解碼器中。利用轉換矩陣本身的對稱性質，就可以有效率地簡化原本繁複的矩陣乘法運算，藉由此結果，在硬體設計上並不需要使用到乘法器即可完成所需的反轉換運算。在此架構中，只需要使用移位器以及加/減法器，即可快速地完成H.264/AVC，VC-1以及AVS所定義的一維反轉換運算。
在模擬之後顯示，所提出的H.264/AVC解碼核心之架構所需的面積是14.1 k的邏輯閘，而最大的操作頻率可以到達130 MHz。這樣的處理速度可以達到即時處理4:2:0 的格式、每秒30 張、畫面解析度為4VGA 大小的影像。另一方面，所提出的多標準反轉換架構所需的邏輯閘數目為8,983，此邏輯閘數量遠少於沒有使用硬體共享的架構。當與個別標準的硬體設計相比時，此架構能減少約一半的邏輯閘數量。

The video coding systems such as ITU-T VCEG and MPEG H.264/AVC, Microsoft VC-1, and Chinese AVS are currently popular standards for multimedia applications. In H.264/AVC, the required components for decoding the residual data consist of CAVLC decoder, inverse quantizer, and inverse transform. Since the decoding speed of these components is varied, the interface should be designed carefully to buffer the data among them. To efficiently realize the interface of the CAVLC decoder and inverse quantizer, the residual decoding procedure in the H.264/AVC is analyzed. After proper arrangement of the CAVLC decoding and inverse quantization procedures, the proposed architecture requires only one inverse quantizer which is further combined into the CAVLC decoder to reduce the buffer size. Moreover, low-cost architectures for computing the multiple H.264/AVC inverse transforms in all profiles are also proposed.
Hardware designs that can support multiple standards are required for versatile media players. This dissertation also proposes a unified inverse transform architecture that can be efficiently used in MPEG and ITU-T H.264/AVC, Microsoft VC-1, and Chinese AVS decoders. For the H.264/AVC 8-point and 4-point inverse transforms, the computational complexity in the proposed architecture is similar to that defined in the H.264/AVC standard. By using the symmetry of the transform matrices, the matrix product operations of the inverse transforms in VC-1 and AVS are efficiently decomposed to only use shifters, adders, and subtractors. All the computations are verified and designed using a hardware unit to achieve a low-cost hardware kernel. The proposed multiple-transform architecture contains fast 1-D transforms and rounding operations for the computation of H.264/AVC, VC-1, and AVS 8-point and 4-point inverse transforms.
Simulation results show that the total implemented gate counts is 14.1 k and the maximum operation frequency is 130 MHz in the proposed H.264/AVC decoding kernel design. It can support the real-time requirement for the 4VGA @30 fps video resolution in 4:2:0 formats. The total number of gates for the proposed multi-standard inverse transform architecture is 8,983, which is much less than that required for architectures without hardware sharing. Compared to individual designs, the proposed architecture reduces the number of logic gates by a factor of two with a penalty of 20% in data throughput.

Abstract (Chinese)...i
Abstract (English)...iii
Acknowledgements...v
Table of Contents...vii
List of Figures...x
List of Tables...xiv
Chapter 1 Introduction...1
1.1 Motivation...1
1.2 Organization for the Dissertation...7
Chapter 2 Overview of H.264/AVC Decoder and Multi-Standard  Inverse Transforms...8
2.1 Overview of H.264/AVC Decoder...8
2.2 CAVLC Coder in H.264/AVC...10
2.2.1 Syntax elements and coding steps...11
2.2.1 A coding example for CAVLC coders...12
2.3 Inverse Quantization in H.264/AVC...15
2.4 DCT-Based Transform Coding...17
2.4.1 H.264/AVC inverse transforms...22
2.4.2 VC-1 inverse transforms...25
2.4.3 AVS inverse transform...26
Chapter 3 Architecture Designs for H.264/AVC Decoder Kernel...28
3.1 Hardware-Oriented Decoding Procedure Modification...28
3.2 Overall Architecture of H.264/AVC Decoder Kernel...32
3.2.1 CAVLC decoder and one IQ component...38
3.2.2 Low-cost inverse transforms architecture for the baseline profile...41
3.2.3 Low-cost inverse transforms architecture for the high profile...45
3.2.4 4 × 4 DC pixel buffer...48
Chapter 4 Architectures for Multi-Standard Inverse Transforms...50
4.1 Overall Architecture for the Unified 1-D Inverse Transform...50
4.2 Data Flow and Architecture for the 8-point Inverse Transforms...54
4.2.1 H.264/AVC 8-point inverse transform...55
4.2.2 VC-1 8-point inverse transform...58
4.2.3 AVS 8-point inverse transform...61
4.3 Data Flow and Architecture for the 4-point and 2-point Inverse  Transforms...64
4.3.1 H.264/AVC 4-point and 2-point inverse transforms...64
4.3.2 VC-1 4-point inverse transform...67
4.4 Rounding Operations for All Inverse Transforms...69
Chapter 5 Simulation Results and Comparisons...70
5.1 Simulations and Comparisons of the H.264/AVC Decoder Kernels...70
5.2 Simulations and Comparisons of the Multi-Standard Inverse Transforms...76
Chapter 6 Conclusions and Future Work...80
6.1 Conclusions...80
6.2 Future Work...81
References...82
Appendix A: Computational Steps of H.264/AVC 8-point Inverse
Transform...88
Appendix B: Computational Steps of VC-1 8-point Inverse Transform...92
Appendix C: Computational Steps of AVS 8-point Inverse Transform...96
Appendix D: Computational Steps of H.264/AVC 4-point Inverse
Transform...100
Appendix E: Computational Steps of VC-1 4-point Inverse Transform...103
Publications...106
                                    

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校內：2013-08-31公開
校外：2014-08-31公開

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