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研究生: 陳人豪
Chen, Jen-hao
論文名稱: 應用於無線感測網路生醫擷取之低電壓低功率三角積分調變器
A Low-Voltage and Low-Power Sigma-Delta Modulator for Bio-Acquisition in Wireless Sensor Network
指導教授: 羅錦興
Luo, Ching-Hsing
黃弘一
Huang, Hong-Yi
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2008
畢業學年度: 96
語文別: 英文
論文頁數: 76
中文關鍵詞: 低功率三角積分調變器
外文關鍵詞: low power, sigma-delta modulator
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  • 近年來,將無線感測網路應用於身體健康監測是未來重點發展之一,由很多感測結點組成一個感測網路,並完成生醫訊號擷取的系統,最後把這個系統微型化成系統晶片。在這些感測結點中,系統晶片所包含的面積與消秏功率是非常關鍵的議題。為了要數位化和監控生醫訊號,輸出訊號需要再經過一級類比轉數位的轉換器。另外,數位輸出訊號將透過無線傳輸到無線感測網路。
    本論文是設計應用於無線感測網路生醫擷取之低電壓低功率二階三角積分調變器,使用由系統到子電路的流程找到最佳化的參數設計。三角積分調變器是使用超取樣64倍,以二級架構的放大器來實現低供應電壓的設計,其中包含交換電容式的積分器、比較器與數位轉類比回授電路。晶片使用台積電0.18 μm 1P6M CMOS標準製程,在頻寬4k Hz、供應電壓1 V的情況下,可以達到八位元的解析度、70 dB的動態範圍與45.3 μW的低功率秏損,經由FoM計算與參考的論文比較,實現了良好的電路效能。

    In recent years, the application of wireless sensor network (WSN) for healthcare monitoring has made significant development. There are lots of sensor nodes which consist of bio-acquired system miniaturized in a single chip. In these nodes, both the system area and the total power consumption are critical issues in the WSN. In order to digitize and monitor the bio-medical signals, the output signal of the amplifier should be further processed by the analog-to-digital converter (ADC). In addition, the digital signal after the ADC could be transmitted by wireless communication system for data transmission in WSN.
    A low-voltage and low-power second order sigma- delta modulator (SDM) with an 11-bit dynamic range for bio-acquired application in wireless sensor network (WSN) is presented. This research uses top-down design flow to find the optimized parameter. A two-stage op amp is optimized for the SDM with over-sampling ratio (OSR) of 64 at low supply voltage. The loop filter of this modulator is realized by using switched capacitor (SC) integrators and simple circuitry consists of comparator and DAC. The test chip is implemented in a 0.18 μm 1P6M CMOS standard process. The post layout simulation reveals that the resolution is 8 bits, dynamic range is over 70 dB and the power consumption of 45.3 μW in the 4 kHz bandwidth under a power supply of 1 V. It is verified that the design has a smaller FoM than the state-of-art.

    Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization 2 Chapter 2 Fundamentals of Sigma-Delta Modulator 4 2.1 Quantization error 4 2.2 Oversampling Technique 6 2.3 Noise-Shaping 8 2.4 First-Order Sigma-Delta Modulators 10 2.5 Second-Order Sigma-Delta Modulators 13 2.6 High-Order Sigma-Delta Modulators 16 2.7 Performance Metrics 17 2.7.1 Resolution 17 2.7.2 Signal-to-Noise Ratio 18 2.7.3 Signal-to-Noise plus Distortion Ratio 18 2.7.4 Dynamic Range 18 Chapter 3 Behavioral Model Simulation of Sigma-Delta Modulator 20 3.1 Design Flow 20 3.2 Bio-Potential Signals 21 3.3 System Ideal Behavioral Model 22 3.4 Non-ideal Model of SDM 23 3.4.1 Clock jitter 23 3.4.2 Switches thermal noise 25 3.4.3 Charge injection 27 3.5 Non-ideal behavioral model of SDM 28 Chapter 4 Design of Low-Voltage Low-Power Sigma-Delta Modulator 31 4.1 System Architecture and Specifications 31 4.2 Switched-Capacitor Integrator 32 4.3 Fully Differential Two-Stage Opamp 35 4.3.1 Circuit Architecture of Opamp 35 4.3.2 Circuit Parameter of Opamp 38 4.4 Comparator 43 4.5 Digital to Analog Converter 45 4.6 Clock Generator 46 4.7 SDM System Simulation Results and Layout 48 4.7.1 SDM System Simulation Results 48 4.7.2 SDM System Layout 54 Chapter 5 Measured Considerations and Results 56 5.1 Measure Consideration 56 5.2 Testing Board 57 5.2.1 First Measurement 57 5.2.2 Second Measurement 60 5.3 Non-ideal Effects 65 5.4 Summary 70 Chapter 6 Conclusions and Future work 72 6.1 Conclusions 72 6.2 Future Works 73 Bibliography 75

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