成功大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	李哿迦 Li, Ke-Chia
論文名稱：	應用於嵌入式系統之節能指令壓縮架構 Energy Efficient Code Compression Architecture for Embedded Processors
指導教授：	陳中和 Chen, Chung-Ho
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering
論文出版年：	2006
畢業學年度：	94
語文別：	中文
論文頁數：	63
中文關鍵詞：	嵌入式系統、指令壓縮
外文關鍵詞：	code compression, embedded system
相關次數：	點閱：67 下載：2
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

由於現今嵌入式系統的設計漸趨複雜，使得耗電量不斷的增加，如何降低系統功耗成了一個重要的問題。採用指令壓縮將能夠藉由減少記憶體傳輸量(memory traffic)來降低整體系統耗電量，因此本文提出了一套指令壓縮架構，將32bit的指令壓縮至16bit。將使得指令存取所造成的記憶體存取總量降低，並且由於處理器的指令提取頻寬加倍，將減少記憶匯流排的動作次數，進而達成降低整體系統功耗的效果。
在系統架構上，本文採用Post-Cache解壓縮的架構，在I-Cache中存放經過壓縮的指令，將可提升I-Cache使用效率，而減少I-Cache miss次數，亦對降低記憶體傳輸量有幫助。經由執行測試軟體Mibench的實驗結果顯示，本架構將提取指令所造成的記憶體傳輸量成功的降低至未壓縮系統的50.39%，對降低整個嵌入式系統的耗電量有著正面的幫助，並且稍微的提升系統效能3.68%。

Because the design of embedded system turns into more complicated, the problem of power consumption becomes more important. Applying code compression can help lower system power consumption in reducing memory bus traffic. This thesis proposes a code compression architecture that compresses a 32-bit instruction into a 16-bit form, such that the fetch bandwidth of processor will be doubled. It’s obvious that the traffic will be reduced since the bus can transfer more instructions per transaction. So we can reduce overall power consumption of the embedded system via code compression.
Furthermore, we use a Post-Cache decompression architecture to improve I-Cache utilization because the I-Cache stores compressed instructions. The decrease of I-Cache miss times implies that the proposed architecture can also reduce memory traffic. Our results show that memory traffic can be significantly reduced without performance degradation. The proposed scheme achieves 49.61% reduction in memory traffic caused by instruction fetch and provides 3.68% performance gain over the baseline system.

Chapter 1 Introduction......................................................................................1
1 Motivation ................................................................................................................... 1
2 Contribution of the thesis .......................................................................................... 1
3 Organization of the thesis.......................................................................................... 2
Chapter 2 Background and Related Work........................................................3
1 Code compression concept......................................................................................... 3
2 Hardware-Based Code Compression Architecture ................................................. 6
3 Current code compression technology ..................................................................... 8
4 Challenge of code compression ............................................................................... 11
4.1 Memory Relocation Issue.................................................................................... 11
4.2 Inline Data Access............................................................................................... 13
Chapter 3 Implementation of a Code Compression System ..........................14
1 System Architecture Overview................................................................................ 14
2 Code Compression Flow .......................................................................................... 17
3 Decompression Unit ................................................................................................. 19
4 Inline Data Buffer..................................................................................................... 25
5 Fast Dictionary Implementation ............................................................................. 27
5.1 Scheme_1 — Static Table ................................................................................... 27
5.2 Scheme_2 — Dynamic Table.............................................................................. 30
5.3 Scheme_3 — Hybrid Table ................................................................................. 33
Chapter 4 Simulation and Verification...........................................................35
1 Simulation Environment.......................................................................................... 35
2 Benchmark................................................................................................................ 37
3 Experimental Result................................................................................................. 39
3.1 Compression Ratio .............................................................................................. 39
3.2 Result of Scheme 1 - Static Table........................................................................ 40
3.3 Result of Scheme 2 - Dynamic Table.................................................................. 45
VI
3.4 Result of Scheme 3 - Hybrid Table ..................................................................... 49
3.5 Expanded Instruction Buffer ............................................................................... 54
4 Overall Cost and Performance Evaluation............................................................ 58
Chapter 5 Conclusion and Future Works.......................................................61
1 Conclusion................................................................................................................. 61
2 Future Works............................................................................................................ 62
                                    

[1] F. Vahid, “Power Estimator Development for Embedded System Memory Tuning,” Journal of Circuits, Systems, and Computers, Vol. 11, No. 5, pages. 459-476, October 2002.
[2] L. Benini, F. Menichelli, and M. Olivieri, “A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems,” IEEE Transactions on Computers, Volume 53, No.4, April 2004.
[3] C. Lefurgy, “Efficient Execution of Compressed Programs,” Ph.D. dissertation, University of Michigan, 2000.
[4] T. Bell, J. Cleary, and I. Witten, “Text Compression,” Prentice Hall, 1990.
[5] Y. Xie, W. Wolf, H. Lekatsas, “Profile-driven Selective Code Compression,” IEEE Design, Automation and Test in Europe Conference and Exhibition, 2003.
[6] H. Lekatsas, “Code Compression for Embedded Systems,” Ph.D. dissertation, Princeton University, 2000.
[7] IBM, “CodePack PowerPC Code Compression Utility User’s Manual Version 3.0,” IBM, 1998.
[8] ARM Ltd. “ARM7TDMI Technical Manual,” http://www.arm.com, 2001.
[9] MIPS Technology, “MIPS32® Architecture for Programmers Volume II: The MIPS32® Instruction Set,” http://www.mips.com, 2001.
[10] Advanced RISC Machines Ltd., “An Introduction to Thumb,” March 1995.
[11] A. Wolfe, A. Chanin, “Executing Compressed Programs on An Embedded RISC Architecture,” Proceedings 25th International Symposium on Microarchitecture, pages 81-91, December 1992.
[12] A. C. Cheng, and G. S. Tyson, “An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs,” IEEE Transactions on Computers, Volume 54, Issue 6, pages. 698 – 713, June 2005.
[13] D. Burger, and T. Austin, “The SimpleScalar Tool Set, Version 2.0,” Computer Architecture News 25(3), pages. 13-25, June 1997.
[14] ARM Ltd. “ARM ELF File Format,” http://www.arm.com, 1997.
[15] SimpleScalar LLC, “SimpleScalar ARM Announce ,“ http://www.eecs.umich.edu/~taustin/code/arm/ANNOUNCE.ARM, 2001.
[16] M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown, “MiBench: A free, commercially representative embedded benchmark suite,” IEEE 4th Annual Workshop on Workload Characterization, Austin, TX, December 2001.

校內：2007-08-30公開
校外：2007-08-30公開

簡易檢索 / 詳目顯示

相關論文