整合於影像感測晶片內的類比數位轉換器，隨著影像數位化的未來趨勢，多需要達到高解度與差不多每秒1~2百萬取樣的規格要求，在此要求下能將消除定態雜訊的相關取樣電路整合的遞迴式架構為最好的選擇。
傳統使用於影像感測晶片內的相關取樣與遞迴式類比數位轉換電路共需3個運算放大器與12個取樣電容。運算放大器部份，1個使用於相關取樣，另外2個使用於遞迴式類比數位轉換。在現今越來越要求低功率消耗與低晶片面積消耗的要求下，逐漸變的不符合需求。
本論文內容提供理論、設計、實作與測試，使用1個運算放大器與8個取樣電容，將相關取樣電路與遞迴式12位元類比數位轉換器整合，且在使用的運算放大器規格要求不需提高的條件下，達到節省功率消耗與晶片面積消耗的目的。因為只使用一個運算放大器完成電路操作，所以將會使其沒有重置的相位來平衡偏移誤差與增益誤差，如此這2種誤差將被一直放大，直到運算放大器輸出端飽和。本論文提供的解決辦法為將輸出端交叉取樣，來抑制輸出端的誤差維持在原來的大小不被放大。
本論文實作的晶片，主要是應用HDTV之上，有另外將64×64的APS像素陣列放入晶片，以供測試。採用TSMC 0.35 μm Mixed-Signal 2P4M Polycide 3.3/5V製程，晶片面積 2.474329 mm2 ，相素相關取樣電路與類比數位轉換器之ENOB大於 11‐bit，全晶片消耗功率2.257mW。

The analog image sensing circuitry and the A/D converter to support today’s requirement have to process 1 to 2 millions pixels per second. To cope with this high through-put demand, a cyclic Correlated Double Sampling (CDS) circuit with the fixed pattern noise removal would be the best choice.
The correlated double sampling circuit and cyclic ADC used in previous image sensors require 3 Opamp (one used in sampling and two used in the cyclic loop) and 12 sampling capacitors. They could incur large power consumption and area, which does not meet today’s requirement as power and area are the primary design concerns. Therefore, design techniques needing fewer Opmap or capacitors but still keeping the same level of noise rejection have been widely researched.
In this thesis, theory, design, implementation, and testing of a novel one-Opmap-and-8-capacitor CDS cyclic circuitry used in 12-bit image sensor will be presented and discussed. It achieves the same resolution as previous with less power consumption and area. However, because there is only one Opamp, the reset phase, offset error, and gain error could potentially accumulate until the sensing circuitry saturates. In this thesis, a novel feedback signal polarity inverting (FSPI) technique is proposed to reduce the noise accumulation. We show the error is kept at the same level as the previous 3 Opamp approach.
The 12-bit sensors introduced in the thesis may be used in HDTV application. A 64x64 APS pixel array made of the sensors is implemented in a chip for testing. TSMC 0.35u Mixed-Signal 2P4M Polycide 3.3/5V process is used and the chip occupies 2.474329 mm2 and consumes 2.257mW. The ENOB is greater than 11-bit.

[1] Chun-Ching. Wang, “A Study of CMOS Technologies for Image Sensor Applications,” PhD Theses, Massachusetts Institute of Technology, August 2001.
[2] Decker. S. J, “Wide Dynamic Range Imager with Parallel On-chip Analog/Digital Output ,” PhD Theses, Massachusetts Institute of Technology, August 1997.
[3] Acosta-Serafini. P, “Predictive Multiple Sampling Algorithm with Overlapping Integration Intervals for Linear Wide Dynamic Range Integrating Image Sensors,” PhD Theses, Massachusetts Institute of Technology, February 2004.
[4] Shinya. Itoh, Shoji. Kawahito, Tomoyuki. Akahori, Susumu. Terakawa, “ Design and implementation of a one-chip wireless camera device for a capsule endoscope,” Proceedings of SPIE, vol.5677, pp.109-118, March. 2005.
[5] Mase. M, Kawahito. S, Sasaki. M, Wakamori. Y, Furuta. M, “ A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters ,” IEEE Journal of Solid-State Circuits, vol.40, no. 12, pp.2787-2795, Dec. 2005.
[6] Furuta. M, Kawahito. S, Inoue. T, Nishikawa. Y, “ A Cyclic A/D converter with pixel noise and column-wise offset canceling for CMOS image sensors ,” Proceedings of 31st ESSCIRC , pp.411-414, Sept. 2005.
[7] Byung-Moo. Min, Peter Kim, Frederick W. Bowman, III, David M. Boisvert, Arlo J. Aude, “ A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC ,” IEEE Journal of Solid-State Circuits, vol.38, no. 12, pp.2031-2039, Dec. 2003.
[8] T. Cho, “Low-Power Low-Voltage Analog-to-Digital Conversion Techniques using Pipelined Architecures ,” PhD Thesis University of California Berkeley, 1995.
[9] D. Cline, “Noise, Speed, and Power Trade-Offs in Pipelined Analog to Digital Converters ,” PhD Thesis University of California Berkeley, 1995.
[10] A. Abo, “Design for Reliability of Low-voltage, Switched-capacitor Circuits ,” PhD Thesis University of California Berkeley, 1999.
[11] Y. Chiu, “High-Performance Pipeline A/D Converter Design in Deep-Submicro CMOS ,” PhD Thesis University of California Berkeley, 2004.

[12] T. Sepke, “Comparator Design and Analysis for Comparator-Based Switched- Capacitor Circuits ,” PhD Theses, Massachusetts Institute of Technology, September 2006.
[13] 鄭光偉, “A 1.0-V, 10-Bit CMOS Pipelined Analog-to-Digital Converter,” Master Thesis, NTU, 2002.
[14] 劉鴻志, “Background Calibration Techniques for Pipelined Analog-to-Digital Converters,” PhD Thesis, NCTU, 2005.
[15] Furuta. M, Nishikawa. Y, Inoue. T, Kawahito. S, “A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters,” IEEE Journal of Solid-State Circuits, vol.42, no. 4, pp.766-774, April. 2007.