LaGdO3 (LGO)有高介電常數、高能隙、低漏電流、熱穩定性佳等優點，且與矽之間有很高的導電帶能障(Conduction band offset)與價電帶能障(Valence band offset)。這些優異的特性使LGO薄膜有機會在邏輯電路、記憶體元件等領域取代現有材料。本研究以射頻磁控濺鍍法於矽基板上沉積LGO薄膜，並以電子束蒸鍍(E-beam evaporation)電極，形成金屬-氧化物-半導體(Metal-oxide-semiconductor, MOS)結構。並以此結構探討製程條件與上電極材料對元件之影響。
實驗第一部分探討薄膜後退火對薄膜特性的影響。退火的過程可以修補薄膜中的缺陷並改善結晶性。元件經過600 oC退火處理後漏電流可降低至1×10-9A以下(於電場強度1MV/cm時)，且擁有較低的等效氧化層電荷密度。若提高退火溫度至700oC，漏電流密度與等效氧化層電荷密度皆會略微提高。
第二部分討論以濺鍍法沉積LGO薄膜時，通入氣體比例(Ar/O2)對薄膜以及元件特性的影響。由實驗結果得知沉積LGO薄膜時通入氣體比例
II
將明顯影響薄膜品質：在通入O2比例10%時，LGO薄膜可因獲得適度修補而呈現較佳介電特性；當通入O2比例大於20%時，濺鍍過程中未被解離的O2會使電漿的平均自由路徑降低，進而影響薄膜品質。
第三部分將討論金屬-氧化物-半導體電容中的上電極材料選擇與薄膜品質及元件特性之關係。本實驗中使用Al/LGO/Si、Ti/LGO/Si與Pt/Ti/LGO/Si等三種不同結構，以驗證上電極材料之對元件電特性的影響。由電容-電壓量測可明顯觀察到Al/LGO/Si元件所量測而得的等效電容值小於Ti/LGO/Si與Pt/Ti/LGO/Si。由TEM結果可觀察到Al/LGO介面存在約20 nm的AlOx界面層，導致以Al/LGO/Si元件電容值偏低。實驗更觀察到具有高度活性的Al、Ti金屬內部皆存在大量氧成分，推測Al、Ti金屬會與LGO薄膜產生反應，並吸收LGO薄膜所釋放出的氧離子，使LGO內部氧空缺增加。因此，Pt/Ti/LGO/Si元件較其他兩種樣品具有更少的氧化物缺陷密度以及邊界缺陷，同時降低漏電流密度的大小以及電容-電壓遲滯效應的影響。

Careful selection of process conditions was the key to influence interface quality in rare earth-based MOS gate. The first part of this study, post-annealing temperature of LGO thin-film was discussed. The equivalent dielectric constant and effective oxide charge of the LGO/Si stacks were both optimized by 600oC-annealing. The second part of this study, sputtering atmosphere Ar/O2 ratio was discussed. LGO film deposited in 10% oxygen ratio showed higher effective dielectric constant, smaller flat-band voltage shift, less effective oxide charge, and breakdown field > 5MV/cm. The third part of this study, different top electrodes was discussed. The clear interfacial layer (AlOx ~20nm) in Al/LGO interface was observed by TEM. The formation of the low-k (k~8.9) AlOx layer was considered not only reduce the dielectric constant but generate more defect. Instead, the influence of interfacial layer could be suppressed by using passive metal as top electrodes. For instance, Pt/Ti/LGO/Si structure showed higher dielectric constant 17.3, less effective oxide charge 6.55×10-11 C, and the hysteresis voltage was 32 mV which was comparable to the films deposited by PLD.

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