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研究生： 周秉勳
Chou, Ping-Hsun
論文名稱： 以零點跨越為基礎之非同步時脈控制高效能管線式逐漸趨近式類比數位轉換器
Power-Efficient Zero Crossing Based Pipelined Successive-Approximation-Register ADC with Asynchronous Timing Control
指導教授： 劉濱達
Liu, Bin-Da
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2014
畢業學年度： 102
語文別： 英文
論文頁數： 97
中文關鍵詞： 管線式類比數位轉換器 、以零點跨越為基礎 、非同步時脈控制
外文關鍵詞： Pipelined SAR ADC, zero crossing based, asynchronous timing control
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    • 本論文提出一個適用於無線通訊系統之管線式逐漸趨近式類比數位轉換器，此轉換器使用非同步時脈控制技術來降低功率消耗及提升殘值放大的速度；此外，利用零點跨越的概念來設計，來達到高速操作與低功率消耗目標，此外並結合快速預先充電的技巧，以更進一步提升轉換速度。本管線式逐漸趨近類比數位轉換器包含一個五位元及一個六位元的逐漸趨近式類比數位轉換器，利用數位錯誤校正技術，以其中一位元做為多餘位元，來放寬此類比數位轉換器中第一級比較器的誤差需求。電路實現方面，與傳統架構相比，所採用的增益級數位類比轉換器之增益為其四分之一，可大幅降低其輸出擺幅及對電流源的線性度要求。再者，本論文也提出了部分電容切換架構，來避免因增益級數位類比轉換器增益縮小所需的額外參考電壓。
    本設計以台灣積體電路公司90奈米一層多晶矽九層金屬導線CMOS製程實現。佈局後模擬結果如下：在取樣頻率為125 MHz時，噪訊比為56.86 dB，整體功率消耗為1.78 mW，經換算此電路的能量消耗指標為0.025 pJ/conversion。

    In this thesis, a pipelined SAR ADC for wireless communication application is proposed. The proposed ADC is designed in the zero crossing based MDAC topology to achieve the features of high-speed and low-power consumption. In addition, the asynchronous timing control technique is utilized to reduce power consumption and enhance the operation speed. The pseudo differential zero crossing based MDAC with fast pre-charging technique is presented to improve the conversion rate and the amplification accuracy. The proposed pipelined SAR ADC consists of a five-bit and a six-bit SAR ADC with one bit for redundancy. Digital error correction technique is adopted to release the comparator offset requirement of the first stage SAR ADC. In circuit implementation, the quarter-gain MDAC is designed to greatly reduce the output swing of MDAC. Furthermore, the partial capacitor switching technique is proposed to compensate the quarter-gain of MDAC for avoiding the use of the extra reference voltage.
    This pipelined SAR ADC is implemented by 90-nm 1P9M CMOS technology. The post-layout simulation shows that the SNDR is 56.86 dB with sampling frequency of 125 MHz. The power dissipation is 1.78 mW and the Figure-of-Merit (FoM) is 0.025 pJ/conversion.

    Abstract (Chinese) i Abstract (English) iii Acknowledgement v Table of Contents vii List of Tables ix List of Figures xi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization of the Thesis 3 Chapter 2 Fundamental Concept of Analog-to-Digital Converter 5 2.1 Introduction of analog-to-digital converter 5 2.1.1 Nyquist-rate ADC 7 2.1.2 Oversampling ADC 8 2.2 Introduction of Pipeline ADC 9 2.2.1 Front-end sample-and-hold 12 2.2.2 Sub-ADC 14 2.2.3 Multiplying digital-to-analog converter 15 2.2.4 Digital error correction 18 2.3 Introduction of Successive Approximation Register (SAR) ADC 21 2.3.1 Asynchronous processing method 23 2.3.2 The switching procedure of SAR ADC 25 2.4 Introduction of Pipelined SAR ADC 31 Chapter 3 Design of An Asynchronous Pseudo-Differential Zero-Crossing Based Pipelined-SAR ADC 37 3.1 Architecture Consideration 38 3.1.1 Zero-crossing based MDAC 38 3.1.2 The asynchronous operation topology 48 3.1.3 Fast pre-charging technique 50 3.2 Proposed Asynchronous Pseudo-Differential Zero-Crossing Based Pipelined SAR ADC 53 Chapter 4 Implementation in Circuit Level 57 4.1 SAR ADCs 58 4.1.1 Bootstrapped switch 58 4.1.2 Switching method of first stage SAR ADC 60 4.1.3 Switching method of second stage SAR ADC 63 4.1.4 Capacitor DAC array 66 4.1.5 SAR logic 68 4.2 Proposed Zero Crossing Based MDAC 73 4.3 Digital Error Correction 76 4.4 Simulation Result 77 4.4.1 Behavior model simulation result 77 4.4.2 Circuit level simulation result 79 4.5 Measurement Results and Discussion 85 Chapter 5 Conclusions and Future Work 89 5.1 Conclusions 89 5.2 Future Work 91 References 93 Biography and Awards 97

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